mirror of
https://repo.dactyloidae.xyz/Dactyloidae/UXP.git
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222 lines
8.5 KiB
C
222 lines
8.5 KiB
C
/*
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* Copyright (c) 2016, Alliance for Open Media. All rights reserved
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*
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* This source code is subject to the terms of the BSD 2 Clause License and
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* the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
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* was not distributed with this source code in the LICENSE file, you can
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* obtain it at www.aomedia.org/license/software. If the Alliance for Open
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* Media Patent License 1.0 was not distributed with this source code in the
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* PATENTS file, you can obtain it at www.aomedia.org/license/patent.
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*/
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#include <assert.h>
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#include <stdio.h>
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#include "config/aom_dsp_rtcd.h"
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#include "aom_dsp/mips/convolve_common_dspr2.h"
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#include "aom_dsp/aom_dsp_common.h"
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#include "aom_dsp/aom_filter.h"
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#include "aom_ports/mem.h"
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#if HAVE_DSPR2
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void aom_convolve_copy_dspr2(const uint8_t *src, ptrdiff_t src_stride,
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uint8_t *dst, ptrdiff_t dst_stride,
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const int16_t *filter_x, int filter_x_stride,
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const int16_t *filter_y, int filter_y_stride,
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int w, int h) {
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int x, y;
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(void)filter_x;
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(void)filter_x_stride;
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(void)filter_y;
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(void)filter_y_stride;
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/* prefetch data to cache memory */
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prefetch_load(src);
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prefetch_load(src + 32);
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prefetch_store(dst);
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switch (w) {
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case 4: {
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uint32_t tp1;
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/* 1 word storage */
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for (y = h; y--;) {
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prefetch_load(src + src_stride);
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prefetch_load(src + src_stride + 32);
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prefetch_store(dst + dst_stride);
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__asm__ __volatile__(
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"ulw %[tp1], (%[src]) \n\t"
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"sw %[tp1], (%[dst]) \n\t" /* store */
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: [tp1] "=&r"(tp1)
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: [src] "r"(src), [dst] "r"(dst));
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src += src_stride;
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dst += dst_stride;
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}
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} break;
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case 8: {
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uint32_t tp1, tp2;
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/* 2 word storage */
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for (y = h; y--;) {
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prefetch_load(src + src_stride);
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prefetch_load(src + src_stride + 32);
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prefetch_store(dst + dst_stride);
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__asm__ __volatile__(
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"ulw %[tp1], 0(%[src]) \n\t"
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"ulw %[tp2], 4(%[src]) \n\t"
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"sw %[tp1], 0(%[dst]) \n\t" /* store */
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"sw %[tp2], 4(%[dst]) \n\t" /* store */
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: [tp1] "=&r"(tp1), [tp2] "=&r"(tp2)
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: [src] "r"(src), [dst] "r"(dst));
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src += src_stride;
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dst += dst_stride;
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}
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} break;
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case 16: {
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uint32_t tp1, tp2, tp3, tp4;
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/* 4 word storage */
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for (y = h; y--;) {
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prefetch_load(src + src_stride);
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prefetch_load(src + src_stride + 32);
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prefetch_store(dst + dst_stride);
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__asm__ __volatile__(
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"ulw %[tp1], 0(%[src]) \n\t"
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"ulw %[tp2], 4(%[src]) \n\t"
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"ulw %[tp3], 8(%[src]) \n\t"
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"ulw %[tp4], 12(%[src]) \n\t"
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"sw %[tp1], 0(%[dst]) \n\t" /* store */
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"sw %[tp2], 4(%[dst]) \n\t" /* store */
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"sw %[tp3], 8(%[dst]) \n\t" /* store */
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"sw %[tp4], 12(%[dst]) \n\t" /* store */
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: [tp1] "=&r"(tp1), [tp2] "=&r"(tp2), [tp3] "=&r"(tp3),
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[tp4] "=&r"(tp4)
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: [src] "r"(src), [dst] "r"(dst));
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src += src_stride;
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dst += dst_stride;
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}
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} break;
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case 32: {
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uint32_t tp1, tp2, tp3, tp4;
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uint32_t tp5, tp6, tp7, tp8;
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/* 8 word storage */
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for (y = h; y--;) {
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prefetch_load(src + src_stride);
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prefetch_load(src + src_stride + 32);
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prefetch_store(dst + dst_stride);
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__asm__ __volatile__(
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"ulw %[tp1], 0(%[src]) \n\t"
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"ulw %[tp2], 4(%[src]) \n\t"
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"ulw %[tp3], 8(%[src]) \n\t"
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"ulw %[tp4], 12(%[src]) \n\t"
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"ulw %[tp5], 16(%[src]) \n\t"
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"ulw %[tp6], 20(%[src]) \n\t"
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"ulw %[tp7], 24(%[src]) \n\t"
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"ulw %[tp8], 28(%[src]) \n\t"
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"sw %[tp1], 0(%[dst]) \n\t" /* store */
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"sw %[tp2], 4(%[dst]) \n\t" /* store */
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"sw %[tp3], 8(%[dst]) \n\t" /* store */
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"sw %[tp4], 12(%[dst]) \n\t" /* store */
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"sw %[tp5], 16(%[dst]) \n\t" /* store */
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"sw %[tp6], 20(%[dst]) \n\t" /* store */
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"sw %[tp7], 24(%[dst]) \n\t" /* store */
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"sw %[tp8], 28(%[dst]) \n\t" /* store */
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: [tp1] "=&r"(tp1), [tp2] "=&r"(tp2), [tp3] "=&r"(tp3),
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[tp4] "=&r"(tp4), [tp5] "=&r"(tp5), [tp6] "=&r"(tp6),
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[tp7] "=&r"(tp7), [tp8] "=&r"(tp8)
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: [src] "r"(src), [dst] "r"(dst));
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src += src_stride;
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dst += dst_stride;
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}
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} break;
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case 64: {
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uint32_t tp1, tp2, tp3, tp4;
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uint32_t tp5, tp6, tp7, tp8;
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prefetch_load(src + 64);
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prefetch_store(dst + 32);
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/* 16 word storage */
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for (y = h; y--;) {
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prefetch_load(src + src_stride);
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prefetch_load(src + src_stride + 32);
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prefetch_load(src + src_stride + 64);
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prefetch_store(dst + dst_stride);
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prefetch_store(dst + dst_stride + 32);
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__asm__ __volatile__(
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"ulw %[tp1], 0(%[src]) \n\t"
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"ulw %[tp2], 4(%[src]) \n\t"
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"ulw %[tp3], 8(%[src]) \n\t"
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"ulw %[tp4], 12(%[src]) \n\t"
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"ulw %[tp5], 16(%[src]) \n\t"
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"ulw %[tp6], 20(%[src]) \n\t"
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"ulw %[tp7], 24(%[src]) \n\t"
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"ulw %[tp8], 28(%[src]) \n\t"
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"sw %[tp1], 0(%[dst]) \n\t" /* store */
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"sw %[tp2], 4(%[dst]) \n\t" /* store */
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"sw %[tp3], 8(%[dst]) \n\t" /* store */
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"sw %[tp4], 12(%[dst]) \n\t" /* store */
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"sw %[tp5], 16(%[dst]) \n\t" /* store */
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"sw %[tp6], 20(%[dst]) \n\t" /* store */
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"sw %[tp7], 24(%[dst]) \n\t" /* store */
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"sw %[tp8], 28(%[dst]) \n\t" /* store */
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"ulw %[tp1], 32(%[src]) \n\t"
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"ulw %[tp2], 36(%[src]) \n\t"
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"ulw %[tp3], 40(%[src]) \n\t"
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"ulw %[tp4], 44(%[src]) \n\t"
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"ulw %[tp5], 48(%[src]) \n\t"
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"ulw %[tp6], 52(%[src]) \n\t"
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"ulw %[tp7], 56(%[src]) \n\t"
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"ulw %[tp8], 60(%[src]) \n\t"
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"sw %[tp1], 32(%[dst]) \n\t" /* store */
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"sw %[tp2], 36(%[dst]) \n\t" /* store */
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"sw %[tp3], 40(%[dst]) \n\t" /* store */
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"sw %[tp4], 44(%[dst]) \n\t" /* store */
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"sw %[tp5], 48(%[dst]) \n\t" /* store */
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"sw %[tp6], 52(%[dst]) \n\t" /* store */
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"sw %[tp7], 56(%[dst]) \n\t" /* store */
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"sw %[tp8], 60(%[dst]) \n\t" /* store */
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: [tp1] "=&r"(tp1), [tp2] "=&r"(tp2), [tp3] "=&r"(tp3),
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[tp4] "=&r"(tp4), [tp5] "=&r"(tp5), [tp6] "=&r"(tp6),
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[tp7] "=&r"(tp7), [tp8] "=&r"(tp8)
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: [src] "r"(src), [dst] "r"(dst));
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src += src_stride;
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dst += dst_stride;
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}
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} break;
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default:
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for (y = h; y--;) {
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for (x = 0; x < w; ++x) {
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dst[x] = src[x];
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}
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src += src_stride;
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dst += dst_stride;
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}
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break;
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}
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}
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#endif
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