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Import aom library
This is the reference implementation for the Alliance for Open Media's av1 video code. The commit used was 4d668d7feb1f8abd809d1bca0418570a7f142a36.
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Roy Tam
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345
third_party/aom/aom_dsp/x86/sad_sse2.asm
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345
third_party/aom/aom_dsp/x86/sad_sse2.asm
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;
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; Copyright (c) 2016, Alliance for Open Media. All rights reserved
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;
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; This source code is subject to the terms of the BSD 2 Clause License and
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; the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
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; was not distributed with this source code in the LICENSE file, you can
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; obtain it at www.aomedia.org/license/software. If the Alliance for Open
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; Media Patent License 1.0 was not distributed with this source code in the
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; PATENTS file, you can obtain it at www.aomedia.org/license/patent.
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;
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;
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%include "third_party/x86inc/x86inc.asm"
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SECTION .text
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%macro SAD_FN 4
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%if %4 == 0
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%if %3 == 5
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cglobal sad%1x%2, 4, %3, 5, src, src_stride, ref, ref_stride, n_rows
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%else ; %3 == 7
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cglobal sad%1x%2, 4, %3, 6, src, src_stride, ref, ref_stride, \
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src_stride3, ref_stride3, n_rows
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%endif ; %3 == 5/7
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%else ; avg
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%if %3 == 5
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cglobal sad%1x%2_avg, 5, 1 + %3, 5, src, src_stride, ref, ref_stride, \
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second_pred, n_rows
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%else ; %3 == 7
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cglobal sad%1x%2_avg, 5, ARCH_X86_64 + %3, 6, src, src_stride, \
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ref, ref_stride, \
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second_pred, \
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src_stride3, ref_stride3
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%if ARCH_X86_64
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%define n_rowsd r7d
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%else ; x86-32
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%define n_rowsd dword r0m
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%endif ; x86-32/64
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%endif ; %3 == 5/7
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%endif ; avg/sad
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movsxdifnidn src_strideq, src_strided
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movsxdifnidn ref_strideq, ref_strided
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%if %3 == 7
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lea src_stride3q, [src_strideq*3]
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lea ref_stride3q, [ref_strideq*3]
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%endif ; %3 == 7
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%endmacro
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%if CONFIG_EXT_PARTITION
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; unsigned int aom_sad128x128_sse2(uint8_t *src, int src_stride,
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; uint8_t *ref, int ref_stride);
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%macro SAD128XN 1-2 0
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SAD_FN 128, %1, 5, %2
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mov n_rowsd, %1
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pxor m0, m0
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.loop:
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movu m1, [refq]
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movu m2, [refq+16]
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movu m3, [refq+32]
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movu m4, [refq+48]
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%if %2 == 1
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pavgb m1, [second_predq+mmsize*0]
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pavgb m2, [second_predq+mmsize*1]
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pavgb m3, [second_predq+mmsize*2]
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pavgb m4, [second_predq+mmsize*3]
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%endif
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psadbw m1, [srcq]
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psadbw m2, [srcq+16]
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psadbw m3, [srcq+32]
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psadbw m4, [srcq+48]
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paddd m1, m2
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paddd m3, m4
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paddd m0, m1
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paddd m0, m3
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movu m1, [refq+64]
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movu m2, [refq+80]
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movu m3, [refq+96]
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movu m4, [refq+112]
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%if %2 == 1
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pavgb m1, [second_predq+mmsize*4]
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pavgb m2, [second_predq+mmsize*5]
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pavgb m3, [second_predq+mmsize*6]
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pavgb m4, [second_predq+mmsize*7]
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lea second_predq, [second_predq+mmsize*8]
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%endif
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psadbw m1, [srcq+64]
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psadbw m2, [srcq+80]
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psadbw m3, [srcq+96]
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psadbw m4, [srcq+112]
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add refq, ref_strideq
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add srcq, src_strideq
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paddd m1, m2
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paddd m3, m4
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paddd m0, m1
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paddd m0, m3
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sub n_rowsd, 1
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jg .loop
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movhlps m1, m0
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paddd m0, m1
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movd eax, m0
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RET
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%endmacro
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INIT_XMM sse2
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SAD128XN 128 ; sad128x128_sse2
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SAD128XN 128, 1 ; sad128x128_avg_sse2
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SAD128XN 64 ; sad128x64_sse2
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SAD128XN 64, 1 ; sad128x64_avg_sse2
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%endif
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; unsigned int aom_sad64x64_sse2(uint8_t *src, int src_stride,
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; uint8_t *ref, int ref_stride);
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%macro SAD64XN 1-2 0
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SAD_FN 64, %1, 5, %2
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mov n_rowsd, %1
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pxor m0, m0
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.loop:
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movu m1, [refq]
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movu m2, [refq+16]
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movu m3, [refq+32]
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movu m4, [refq+48]
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%if %2 == 1
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pavgb m1, [second_predq+mmsize*0]
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pavgb m2, [second_predq+mmsize*1]
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pavgb m3, [second_predq+mmsize*2]
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pavgb m4, [second_predq+mmsize*3]
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lea second_predq, [second_predq+mmsize*4]
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%endif
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psadbw m1, [srcq]
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psadbw m2, [srcq+16]
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psadbw m3, [srcq+32]
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psadbw m4, [srcq+48]
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paddd m1, m2
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paddd m3, m4
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add refq, ref_strideq
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paddd m0, m1
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add srcq, src_strideq
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paddd m0, m3
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dec n_rowsd
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jg .loop
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movhlps m1, m0
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paddd m0, m1
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movd eax, m0
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RET
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%endmacro
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INIT_XMM sse2
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%if CONFIG_EXT_PARTITION
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SAD64XN 128 ; sad64x128_sse2
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SAD64XN 128, 1 ; sad64x128_avg_sse2
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%endif
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SAD64XN 64 ; sad64x64_sse2
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SAD64XN 32 ; sad64x32_sse2
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SAD64XN 64, 1 ; sad64x64_avg_sse2
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SAD64XN 32, 1 ; sad64x32_avg_sse2
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; unsigned int aom_sad32x32_sse2(uint8_t *src, int src_stride,
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; uint8_t *ref, int ref_stride);
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%macro SAD32XN 1-2 0
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SAD_FN 32, %1, 5, %2
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mov n_rowsd, %1/2
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pxor m0, m0
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.loop:
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movu m1, [refq]
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movu m2, [refq+16]
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movu m3, [refq+ref_strideq]
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movu m4, [refq+ref_strideq+16]
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%if %2 == 1
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pavgb m1, [second_predq+mmsize*0]
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pavgb m2, [second_predq+mmsize*1]
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pavgb m3, [second_predq+mmsize*2]
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pavgb m4, [second_predq+mmsize*3]
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lea second_predq, [second_predq+mmsize*4]
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%endif
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psadbw m1, [srcq]
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psadbw m2, [srcq+16]
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psadbw m3, [srcq+src_strideq]
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psadbw m4, [srcq+src_strideq+16]
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paddd m1, m2
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paddd m3, m4
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lea refq, [refq+ref_strideq*2]
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paddd m0, m1
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lea srcq, [srcq+src_strideq*2]
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paddd m0, m3
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dec n_rowsd
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jg .loop
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movhlps m1, m0
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paddd m0, m1
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movd eax, m0
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RET
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%endmacro
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INIT_XMM sse2
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SAD32XN 64 ; sad32x64_sse2
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SAD32XN 32 ; sad32x32_sse2
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SAD32XN 16 ; sad32x16_sse2
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SAD32XN 64, 1 ; sad32x64_avg_sse2
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SAD32XN 32, 1 ; sad32x32_avg_sse2
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SAD32XN 16, 1 ; sad32x16_avg_sse2
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; unsigned int aom_sad16x{8,16}_sse2(uint8_t *src, int src_stride,
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; uint8_t *ref, int ref_stride);
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%macro SAD16XN 1-2 0
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SAD_FN 16, %1, 7, %2
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mov n_rowsd, %1/4
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pxor m0, m0
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.loop:
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movu m1, [refq]
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movu m2, [refq+ref_strideq]
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movu m3, [refq+ref_strideq*2]
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movu m4, [refq+ref_stride3q]
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%if %2 == 1
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pavgb m1, [second_predq+mmsize*0]
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pavgb m2, [second_predq+mmsize*1]
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pavgb m3, [second_predq+mmsize*2]
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pavgb m4, [second_predq+mmsize*3]
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lea second_predq, [second_predq+mmsize*4]
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%endif
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psadbw m1, [srcq]
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psadbw m2, [srcq+src_strideq]
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psadbw m3, [srcq+src_strideq*2]
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psadbw m4, [srcq+src_stride3q]
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paddd m1, m2
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paddd m3, m4
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lea refq, [refq+ref_strideq*4]
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paddd m0, m1
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lea srcq, [srcq+src_strideq*4]
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paddd m0, m3
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dec n_rowsd
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jg .loop
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movhlps m1, m0
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paddd m0, m1
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movd eax, m0
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RET
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%endmacro
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INIT_XMM sse2
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SAD16XN 32 ; sad16x32_sse2
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SAD16XN 16 ; sad16x16_sse2
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SAD16XN 8 ; sad16x8_sse2
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SAD16XN 32, 1 ; sad16x32_avg_sse2
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SAD16XN 16, 1 ; sad16x16_avg_sse2
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SAD16XN 8, 1 ; sad16x8_avg_sse2
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; unsigned int aom_sad8x{8,16}_sse2(uint8_t *src, int src_stride,
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; uint8_t *ref, int ref_stride);
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%macro SAD8XN 1-2 0
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SAD_FN 8, %1, 7, %2
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mov n_rowsd, %1/4
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pxor m0, m0
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.loop:
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movh m1, [refq]
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movhps m1, [refq+ref_strideq]
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movh m2, [refq+ref_strideq*2]
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movhps m2, [refq+ref_stride3q]
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%if %2 == 1
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pavgb m1, [second_predq+mmsize*0]
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pavgb m2, [second_predq+mmsize*1]
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lea second_predq, [second_predq+mmsize*2]
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%endif
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movh m3, [srcq]
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movhps m3, [srcq+src_strideq]
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movh m4, [srcq+src_strideq*2]
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movhps m4, [srcq+src_stride3q]
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psadbw m1, m3
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psadbw m2, m4
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lea refq, [refq+ref_strideq*4]
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paddd m0, m1
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lea srcq, [srcq+src_strideq*4]
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paddd m0, m2
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dec n_rowsd
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jg .loop
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movhlps m1, m0
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paddd m0, m1
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movd eax, m0
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RET
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%endmacro
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INIT_XMM sse2
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SAD8XN 16 ; sad8x16_sse2
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SAD8XN 8 ; sad8x8_sse2
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SAD8XN 4 ; sad8x4_sse2
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SAD8XN 16, 1 ; sad8x16_avg_sse2
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SAD8XN 8, 1 ; sad8x8_avg_sse2
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SAD8XN 4, 1 ; sad8x4_avg_sse2
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; unsigned int aom_sad4x{4, 8}_sse2(uint8_t *src, int src_stride,
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; uint8_t *ref, int ref_stride);
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%macro SAD4XN 1-2 0
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SAD_FN 4, %1, 7, %2
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mov n_rowsd, %1/4
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pxor m0, m0
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.loop:
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movd m1, [refq]
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movd m2, [refq+ref_strideq]
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movd m3, [refq+ref_strideq*2]
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movd m4, [refq+ref_stride3q]
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punpckldq m1, m2
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punpckldq m3, m4
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movlhps m1, m3
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%if %2 == 1
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pavgb m1, [second_predq+mmsize*0]
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lea second_predq, [second_predq+mmsize*1]
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%endif
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movd m2, [srcq]
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movd m5, [srcq+src_strideq]
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movd m4, [srcq+src_strideq*2]
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movd m3, [srcq+src_stride3q]
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punpckldq m2, m5
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punpckldq m4, m3
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movlhps m2, m4
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psadbw m1, m2
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lea refq, [refq+ref_strideq*4]
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paddd m0, m1
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lea srcq, [srcq+src_strideq*4]
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dec n_rowsd
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jg .loop
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movhlps m1, m0
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paddd m0, m1
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movd eax, m0
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RET
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%endmacro
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INIT_XMM sse2
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SAD4XN 8 ; sad4x8_sse
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SAD4XN 4 ; sad4x4_sse
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SAD4XN 8, 1 ; sad4x8_avg_sse
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SAD4XN 4, 1 ; sad4x4_avg_sse
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