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[ffvpx] Update ffvp9/ffvp8 to 3.4.2-release
Structure of code was slightly modified so that it should be no longer necessary to re-generate the config_*.h files, greatly simplifying the resync process in the future.
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trav90
Roy Tam
parent
705e180aea
commit
d1361d3c21
183 changed files with 17773 additions and 28489 deletions
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@ -847,6 +847,108 @@ DL_FUNCS
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INIT_XMM avx
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DL_FUNCS
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%if HAVE_AVX2_EXTERNAL
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INIT_YMM avx2
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cglobal vp9_ipred_dl_16x16_16, 2, 4, 5, dst, stride, l, a
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movifnidn aq, amp
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mova m0, [aq] ; abcdefghijklmnop
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vpbroadcastw xm1, [aq+30] ; pppppppp
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vperm2i128 m2, m0, m1, q0201 ; ijklmnoppppppppp
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vpalignr m3, m2, m0, 2 ; bcdefghijklmnopp
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vpalignr m4, m2, m0, 4 ; cdefghijklmnoppp
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LOWPASS 0, 3, 4 ; BCDEFGHIJKLMNOPp
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vperm2i128 m2, m0, m1, q0201 ; JKLMNOPppppppppp
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DEFINE_ARGS dst, stride, stride3, cnt
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mov cntd, 2
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lea stride3q, [strideq*3]
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.loop:
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mova [dstq+strideq*0], m0
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vpalignr m3, m2, m0, 2
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vpalignr m4, m2, m0, 4
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mova [dstq+strideq*1], m3
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mova [dstq+strideq*2], m4
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vpalignr m3, m2, m0, 6
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vpalignr m4, m2, m0, 8
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mova [dstq+stride3q ], m3
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lea dstq, [dstq+strideq*4]
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mova [dstq+strideq*0], m4
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vpalignr m3, m2, m0, 10
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vpalignr m4, m2, m0, 12
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mova [dstq+strideq*1], m3
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mova [dstq+strideq*2], m4
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vpalignr m3, m2, m0, 14
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mova [dstq+stride3q ], m3
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lea dstq, [dstq+strideq*4]
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mova m0, m2
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vperm2i128 m2, m2, m2, q0101 ; pppppppppppppppp
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dec cntd
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jg .loop
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RET
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cglobal vp9_ipred_dl_32x32_16, 2, 6, 7, dst, stride, l, a
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movifnidn aq, amp
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mova m0, [aq+mmsize*0+ 0] ; abcdefghijklmnop
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mova m1, [aq+mmsize*1+ 0] ; qrstuvwxyz012345
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vpbroadcastw xm4, [aq+mmsize*1+30] ; 55555555
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vperm2i128 m5, m0, m1, q0201 ; ijklmnopqrstuvwx
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vpalignr m2, m5, m0, 2 ; bcdefghijklmnopq
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vpalignr m3, m5, m0, 4 ; cdefghijklmnopqr
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LOWPASS 0, 2, 3 ; BCDEFGHIJKLMNOPQ
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vperm2i128 m5, m1, m4, q0201 ; yz01234555555555
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vpalignr m2, m5, m1, 2 ; rstuvwxyz0123455
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vpalignr m3, m5, m1, 4 ; stuvwxyz01234555
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LOWPASS 1, 2, 3 ; RSTUVWXYZ......5
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vperm2i128 m2, m1, m4, q0201 ; Z......555555555
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vperm2i128 m5, m0, m1, q0201 ; JKLMNOPQRSTUVWXY
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DEFINE_ARGS dst, stride, stride3, cnt
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lea stride3q, [strideq*3]
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mov cntd, 4
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.loop:
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mova [dstq+strideq*0 + 0], m0
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mova [dstq+strideq*0 +32], m1
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vpalignr m3, m5, m0, 2
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vpalignr m4, m2, m1, 2
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mova [dstq+strideq*1 + 0], m3
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mova [dstq+strideq*1 +32], m4
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vpalignr m3, m5, m0, 4
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vpalignr m4, m2, m1, 4
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mova [dstq+strideq*2 + 0], m3
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mova [dstq+strideq*2 +32], m4
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vpalignr m3, m5, m0, 6
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vpalignr m4, m2, m1, 6
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mova [dstq+stride3q*1+ 0], m3
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mova [dstq+stride3q*1+32], m4
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lea dstq, [dstq+strideq*4]
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vpalignr m3, m5, m0, 8
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vpalignr m4, m2, m1, 8
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mova [dstq+strideq*0 + 0], m3
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mova [dstq+strideq*0 +32], m4
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vpalignr m3, m5, m0, 10
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vpalignr m4, m2, m1, 10
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mova [dstq+strideq*1 + 0], m3
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mova [dstq+strideq*1 +32], m4
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vpalignr m3, m5, m0, 12
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vpalignr m4, m2, m1, 12
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mova [dstq+strideq*2+ 0], m3
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mova [dstq+strideq*2+32], m4
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vpalignr m3, m5, m0, 14
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vpalignr m4, m2, m1, 14
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mova [dstq+stride3q+ 0], m3
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mova [dstq+stride3q+ 32], m4
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vpalignr m3, m5, m0, 16
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vpalignr m4, m2, m1, 16
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vperm2i128 m5, m3, m4, q0201
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vperm2i128 m2, m4, m4, q0101
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mova m0, m3
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mova m1, m4
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lea dstq, [dstq+strideq*4]
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dec cntd
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jg .loop
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RET
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%endif
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%macro DR_FUNCS 1 ; stack_mem_for_32x32_32bit_function
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cglobal vp9_ipred_dr_4x4_16, 4, 4, 3, dst, stride, l, a
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movh m0, [lq] ; wxyz....
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@ -1068,6 +1170,161 @@ DR_FUNCS 2
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INIT_XMM avx
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DR_FUNCS 2
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%if HAVE_AVX2_EXTERNAL
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INIT_YMM avx2
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cglobal vp9_ipred_dr_16x16_16, 4, 5, 6, dst, stride, l, a
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mova m0, [lq] ; klmnopqrstuvwxyz
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movu m1, [aq-2] ; *abcdefghijklmno
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mova m2, [aq] ; abcdefghijklmnop
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vperm2i128 m4, m2, m2, q2001 ; ijklmnop........
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vpalignr m5, m4, m2, 2 ; bcdefghijklmnop.
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vperm2i128 m3, m0, m1, q0201 ; stuvwxyz*abcdefg
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LOWPASS 1, 2, 5 ; ABCDEFGHIJKLMNO.
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vpalignr m4, m3, m0, 2 ; lmnopqrstuvwxyz*
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vpalignr m5, m3, m0, 4 ; mnopqrstuvwxyz*a
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LOWPASS 0, 4, 5 ; LMNOPQRSTUVWXYZ#
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vperm2i128 m5, m0, m1, q0201 ; TUVWXYZ#ABCDEFGH
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DEFINE_ARGS dst, stride, stride3, stride5, dst3
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lea dst3q, [dstq+strideq*4]
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lea stride3q, [strideq*3]
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lea stride5q, [stride3q+strideq*2]
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vpalignr m3, m5, m0, 2
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vpalignr m4, m1, m5, 2
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mova [dst3q+stride5q*2], m3 ; 14
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mova [ dstq+stride3q*2], m4 ; 6
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vpalignr m3, m5, m0, 4
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vpalignr m4, m1, m5, 4
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sub dst3q, strideq
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mova [dst3q+stride5q*2], m3 ; 13
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mova [dst3q+strideq*2 ], m4 ; 5
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mova [dst3q+stride3q*4], m0 ; 15
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vpalignr m3, m5, m0, 6
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vpalignr m4, m1, m5, 6
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mova [dstq+stride3q*4], m3 ; 12
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mova [dst3q+strideq*1], m4 ; 4
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vpalignr m3, m5, m0, 8
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vpalignr m4, m1, m5, 8
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mova [dst3q+strideq*8], m3 ; 11
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mova [dst3q+strideq*0], m4 ; 3
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vpalignr m3, m5, m0, 10
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vpalignr m4, m1, m5, 10
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mova [dstq+stride5q*2], m3 ; 10
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mova [dstq+strideq*2 ], m4 ; 2
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vpalignr m3, m5, m0, 12
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vpalignr m4, m1, m5, 12
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mova [dst3q+stride3q*2], m3 ; 9
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mova [dstq+strideq*1 ], m4 ; 1
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vpalignr m3, m5, m0, 14
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vpalignr m4, m1, m5, 14
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mova [dstq+strideq*8], m3 ; 8
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mova [dstq+strideq*0], m4 ; 0
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mova [dst3q+strideq*4], m5 ; 7
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RET
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%if ARCH_X86_64
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cglobal vp9_ipred_dr_32x32_16, 4, 7, 10, dst, stride, l, a
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mova m0, [lq+mmsize*0+0] ; l[0-15]
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mova m1, [lq+mmsize*1+0] ; l[16-31]
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movu m2, [aq+mmsize*0-2] ; *abcdefghijklmno
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mova m3, [aq+mmsize*0+0] ; abcdefghijklmnop
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mova m4, [aq+mmsize*1+0] ; qrstuvwxyz012345
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vperm2i128 m5, m0, m1, q0201 ; lmnopqrstuvwxyz0
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vpalignr m6, m5, m0, 2 ; mnopqrstuvwxyz01
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vpalignr m7, m5, m0, 4 ; nopqrstuvwxyz012
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LOWPASS 0, 6, 7 ; L[0-15]
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vperm2i128 m7, m1, m2, q0201 ; stuvwxyz*abcdefg
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vpalignr m5, m7, m1, 2 ; lmnopqrstuvwxyz*
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vpalignr m6, m7, m1, 4 ; mnopqrstuvwxyz*a
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LOWPASS 1, 5, 6 ; L[16-31]#
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vperm2i128 m5, m3, m4, q0201 ; ijklmnopqrstuvwx
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vpalignr m6, m5, m3, 2 ; bcdefghijklmnopq
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LOWPASS 2, 3, 6 ; A[0-15]
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movu m3, [aq+mmsize*1-2] ; pqrstuvwxyz01234
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vperm2i128 m6, m4, m4, q2001 ; yz012345........
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vpalignr m7, m6, m4, 2 ; rstuvwxyz012345.
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LOWPASS 3, 4, 7 ; A[16-31].
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vperm2i128 m4, m1, m2, q0201 ; TUVWXYZ#ABCDEFGH
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vperm2i128 m5, m0, m1, q0201 ; L[7-15]L[16-23]
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vperm2i128 m8, m2, m3, q0201 ; IJKLMNOPQRSTUVWX
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DEFINE_ARGS dst8, stride, stride3, stride7, stride5, dst24, cnt
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lea stride3q, [strideq*3]
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lea stride5q, [stride3q+strideq*2]
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lea stride7q, [strideq*4+stride3q]
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lea dst24q, [dst8q+stride3q*8]
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lea dst8q, [dst8q+strideq*8]
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mov cntd, 2
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.loop:
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mova [dst24q+stride7q+0 ], m0 ; 31 23 15 7
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mova [dst24q+stride7q+32], m1
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mova [dst8q+stride7q+0], m1
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mova [dst8q+stride7q+32], m2
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vpalignr m6, m4, m1, 2
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vpalignr m7, m5, m0, 2
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vpalignr m9, m8, m2, 2
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mova [dst24q+stride3q*2+0], m7 ; 30 22 14 6
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mova [dst24q+stride3q*2+32], m6
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mova [dst8q+stride3q*2+0], m6
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mova [dst8q+stride3q*2+32], m9
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vpalignr m6, m4, m1, 4
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vpalignr m7, m5, m0, 4
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vpalignr m9, m8, m2, 4
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mova [dst24q+stride5q+0], m7 ; 29 21 13 5
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mova [dst24q+stride5q+32], m6
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mova [dst8q+stride5q+0], m6
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mova [dst8q+stride5q+32], m9
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vpalignr m6, m4, m1, 6
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vpalignr m7, m5, m0, 6
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vpalignr m9, m8, m2, 6
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mova [dst24q+strideq*4+0 ], m7 ; 28 20 12 4
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mova [dst24q+strideq*4+32], m6
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mova [dst8q+strideq*4+0], m6
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mova [dst8q+strideq*4+32], m9
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vpalignr m6, m4, m1, 8
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vpalignr m7, m5, m0, 8
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vpalignr m9, m8, m2, 8
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mova [dst24q+stride3q+0 ], m7 ; 27 19 11 3
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mova [dst24q+stride3q+32], m6
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mova [dst8q+stride3q+0], m6
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mova [dst8q+stride3q+32], m9
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vpalignr m6, m4, m1, 10
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vpalignr m7, m5, m0, 10
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vpalignr m9, m8, m2, 10
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mova [dst24q+strideq*2+0 ], m7 ; 26 18 10 2
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mova [dst24q+strideq*2+32], m6
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mova [dst8q+strideq*2+0], m6
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mova [dst8q+strideq*2+32], m9
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vpalignr m6, m4, m1, 12
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vpalignr m7, m5, m0, 12
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vpalignr m9, m8, m2, 12
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mova [dst24q+strideq+0 ], m7 ; 25 17 9 1
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mova [dst24q+strideq+32], m6
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mova [dst8q+strideq+0], m6
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mova [dst8q+strideq+32], m9
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vpalignr m6, m4, m1, 14
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vpalignr m7, m5, m0, 14
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vpalignr m9, m8, m2, 14
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mova [dst24q+strideq*0+0 ], m7 ; 24 16 8 0
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mova [dst24q+strideq*0+32], m6
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mova [dst8q+strideq*0+0], m6
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mova [dst8q+strideq*0+32], m9
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mova m0, m5
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mova m5, m1
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mova m1, m4
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mova m4, m2
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mova m2, m8
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mova m8, m3
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sub dst24q, stride7q
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sub dst24q, strideq
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sub dst8q, stride7q
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sub dst8q, strideq
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dec cntd
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jg .loop
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RET
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%endif
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%endif
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%macro VL_FUNCS 1 ; stack_mem_for_32x32_32bit_function
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cglobal vp9_ipred_vl_4x4_16, 2, 4, 3, dst, stride, l, a
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movifnidn aq, amp
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