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Bug 1330942 - move MemoryAccessDesc::isUnaligned to the ARM/MIPS platform layer

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Tag: #1542
This commit is contained in:
Jiaxun Yang 2020-05-12 12:40:13 +08:00 • committed by Roy Tam
commit ccced44f81
10 changed files with 40 additions and 21 deletions
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12
js/src/jit/arm/Assembler-arm.cpp
View file

@ -171,6 +171,18 @@ ABIArgGenerator::next(MIRType type)
return softNext(type); return softNext(type);
} }
bool
js::jit::IsUnaligned(const wasm::MemoryAccessDesc& access)
{
if (!access.align())
return false;
if (access.type() == Scalar::Float64 && access.align() >= 4)
return false;
return access.align() < access.byteSize();
}
// Encode a standard register when it is being used as src1, the dest, and an // Encode a standard register when it is being used as src1, the dest, and an
// extra register. These should never be called with an InvalidReg. // extra register. These should never be called with an InvalidReg.
uint32_t uint32_t

2
js/src/jit/arm/Assembler-arm.h
View file

@ -108,6 +108,8 @@ class ABIArgGenerator
uint32_t stackBytesConsumedSoFar() const { return stackOffset_; } uint32_t stackBytesConsumedSoFar() const { return stackOffset_; }
}; };
bool IsUnaligned(const wasm::MemoryAccessDesc& access);
static constexpr Register ABINonArgReg0 = r4; static constexpr Register ABINonArgReg0 = r4;
static constexpr Register ABINonArgReg1 = r5; static constexpr Register ABINonArgReg1 = r5;
static constexpr Register ABINonArgReg2 = r6; static constexpr Register ABINonArgReg2 = r6;

4
js/src/jit/arm/Lowering-arm.cpp
View file

@ -613,7 +613,7 @@ LIRGeneratorARM::visitWasmLoad(MWasmLoad* ins)
LAllocation ptr = useRegisterAtStart(base); LAllocation ptr = useRegisterAtStart(base);
if (ins->access().isUnaligned()) { if (IsUnaligned(ins->access())) {
// Unaligned access expected! Revert to a byte load. // Unaligned access expected! Revert to a byte load.
LDefinition ptrCopy = tempCopy(base, 0); LDefinition ptrCopy = tempCopy(base, 0);
@ -662,7 +662,7 @@ LIRGeneratorARM::visitWasmStore(MWasmStore* ins)
LAllocation ptr = useRegisterAtStart(base); LAllocation ptr = useRegisterAtStart(base);
if (ins->access().isUnaligned()) { if (IsUnaligned(ins->access())) {
// Unaligned access expected! Revert to a byte store. // Unaligned access expected! Revert to a byte store.
LDefinition ptrCopy = tempCopy(base, 0); LDefinition ptrCopy = tempCopy(base, 0);

6
js/src/jit/mips-shared/Assembler-mips-shared.h
View file

@ -1547,6 +1547,12 @@ class InstGS : public Instruction
{ } { }
}; };
inline bool
IsUnaligned(const wasm::MemoryAccessDesc& access)
{
return access.align() && access.align() < access.byteSize();
}
} // namespace jit } // namespace jit
} // namespace js } // namespace js

4
js/src/jit/mips-shared/CodeGenerator-mips-shared.cpp
View file

@ -1915,7 +1915,7 @@ CodeGeneratorMIPSShared::emitWasmLoad(T* lir)
BaseIndex address(HeapReg, ptr, TimesOne); BaseIndex address(HeapReg, ptr, TimesOne);
if (mir->access().isUnaligned()) { if (IsUnaligned(mir->access())) {
Register temp = ToRegister(lir->getTemp(1)); Register temp = ToRegister(lir->getTemp(1));
if (isFloat) { if (isFloat) {
@ -2000,7 +2000,7 @@ CodeGeneratorMIPSShared::emitWasmStore(T* lir)
BaseIndex address(HeapReg, ptr, TimesOne); BaseIndex address(HeapReg, ptr, TimesOne);
if (mir->access().isUnaligned()) { if (IsUnaligned(mir->access())) {
Register temp = ToRegister(lir->getTemp(1)); Register temp = ToRegister(lir->getTemp(1));
if (isFloat) { if (isFloat) {

4
js/src/jit/mips-shared/Lowering-mips-shared.cpp
View file

@ -324,7 +324,7 @@ LIRGeneratorMIPSShared::visitWasmLoad(MWasmLoad* ins)
LAllocation ptr = useRegisterAtStart(base); LAllocation ptr = useRegisterAtStart(base);
if (ins->access().isUnaligned()) { if (IsUnaligned(ins->access())) {
if (ins->type() == MIRType::Int64) { if (ins->type() == MIRType::Int64) {
auto* lir = new(alloc()) LWasmUnalignedLoadI64(ptr, temp()); auto* lir = new(alloc()) LWasmUnalignedLoadI64(ptr, temp());
if (ins->access().offset()) if (ins->access().offset())
@ -367,7 +367,7 @@ LIRGeneratorMIPSShared::visitWasmStore(MWasmStore* ins)
MDefinition* value = ins->value(); MDefinition* value = ins->value();
LAllocation baseAlloc = useRegisterAtStart(base); LAllocation baseAlloc = useRegisterAtStart(base);
if (ins->access().isUnaligned()) { if (IsUnaligned(ins->access())) {
if (ins->type() == MIRType::Int64) { if (ins->type() == MIRType::Int64) {
LInt64Allocation valueAlloc = useInt64RegisterAtStart(value); LInt64Allocation valueAlloc = useInt64RegisterAtStart(value);
auto* lir = new(alloc()) LWasmUnalignedStoreI64(baseAlloc, valueAlloc, temp()); auto* lir = new(alloc()) LWasmUnalignedStoreI64(baseAlloc, valueAlloc, temp());

4
js/src/jit/mips32/CodeGenerator-mips32.cpp
View file

@ -490,7 +490,7 @@ CodeGeneratorMIPS::emitWasmLoadI64(T* lir)
masm.memoryBarrier(mir->access().barrierBefore()); masm.memoryBarrier(mir->access().barrierBefore());
MOZ_ASSERT(INT64LOW_OFFSET == 0); MOZ_ASSERT(INT64LOW_OFFSET == 0);
if (mir->access().isUnaligned()) { if (IsUnaligned(mir->access())) {
Register temp = ToRegister(lir->getTemp(1)); Register temp = ToRegister(lir->getTemp(1));
if (byteSize <= 4) { if (byteSize <= 4) {
@ -577,7 +577,7 @@ CodeGeneratorMIPS::emitWasmStoreI64(T* lir)
masm.memoryBarrier(mir->access().barrierBefore()); masm.memoryBarrier(mir->access().barrierBefore());
MOZ_ASSERT(INT64LOW_OFFSET == 0); MOZ_ASSERT(INT64LOW_OFFSET == 0);
if (mir->access().isUnaligned()) { if (IsUnaligned(mir->access())) {
Register temp = ToRegister(lir->getTemp(1)); Register temp = ToRegister(lir->getTemp(1));
if (byteSize <= 4) { if (byteSize <= 4) {

4
js/src/jit/mips64/CodeGenerator-mips64.cpp
View file

@ -449,7 +449,7 @@ CodeGeneratorMIPS64::emitWasmLoadI64(T* lir)
masm.memoryBarrier(mir->access().barrierBefore()); masm.memoryBarrier(mir->access().barrierBefore());
if (mir->access().isUnaligned()) { if (IsUnaligned(mir->access())) {
Register temp = ToRegister(lir->getTemp(1)); Register temp = ToRegister(lir->getTemp(1));
masm.ma_load_unaligned(ToOutRegister64(lir).reg, BaseIndex(HeapReg, ptr, TimesOne), masm.ma_load_unaligned(ToOutRegister64(lir).reg, BaseIndex(HeapReg, ptr, TimesOne),
@ -514,7 +514,7 @@ CodeGeneratorMIPS64::emitWasmStoreI64(T* lir)
masm.memoryBarrier(mir->access().barrierBefore()); masm.memoryBarrier(mir->access().barrierBefore());
if (mir->access().isUnaligned()) { if (IsUnaligned(mir->access())) {
Register temp = ToRegister(lir->getTemp(1)); Register temp = ToRegister(lir->getTemp(1));
masm.ma_store_unaligned(ToRegister64(lir->value()).reg, BaseIndex(HeapReg, ptr, TimesOne), masm.ma_store_unaligned(ToRegister64(lir->value()).reg, BaseIndex(HeapReg, ptr, TimesOne),

1
js/src/jit/shared/Assembler-shared.h
View file

@ -747,7 +747,6 @@ class MemoryAccessDesc
TrapOffset trapOffset() const { return *trapOffset_; } TrapOffset trapOffset() const { return *trapOffset_; }
bool isAtomic() const { return (barrierBefore_ | barrierAfter_) != jit::MembarNobits; } bool isAtomic() const { return (barrierBefore_ | barrierAfter_) != jit::MembarNobits; }
bool isSimd() const { return Scalar::isSimdType(type_); } bool isSimd() const { return Scalar::isSimdType(type_); }
bool isUnaligned() const { return align() && align() < byteSize(); }
bool isPlainAsmJS() const { return !hasTrap(); } bool isPlainAsmJS() const { return !hasTrap(); }
void clearOffset() { offset_ = 0; } void clearOffset() { offset_ = 0; }

20
js/src/wasm/WasmBaselineCompile.cpp
View file

@ -3206,7 +3206,7 @@ class BaseCompiler
// This is the temp register passed as the last argument to load() // This is the temp register passed as the last argument to load()
MOZ_MUST_USE size_t loadStoreTemps(MemoryAccessDesc& access) { MOZ_MUST_USE size_t loadStoreTemps(MemoryAccessDesc& access) {
#if defined(JS_CODEGEN_ARM) #if defined(JS_CODEGEN_ARM)
if (access.isUnaligned()) { if (IsUnaligned(access)) {
switch (access.type()) { switch (access.type()) {
case Scalar::Float32: case Scalar::Float32:
return 1; return 1;
@ -3391,7 +3391,7 @@ class BaseCompiler
#ifdef JS_CODEGEN_ARM #ifdef JS_CODEGEN_ARM
void void
loadI32(MemoryAccessDesc access, bool isSigned, RegI32 ptr, Register rt) { loadI32(MemoryAccessDesc access, bool isSigned, RegI32 ptr, Register rt) {
if (access.byteSize() > 1 && access.isUnaligned()) { if (access.byteSize() > 1 && IsUnaligned(ins->access())) {
masm.add32(HeapReg, ptr.reg); masm.add32(HeapReg, ptr.reg);
SecondScratchRegisterScope scratch(*this); SecondScratchRegisterScope scratch(*this);
masm.emitUnalignedLoad(isSigned, access.byteSize(), ptr.reg, scratch, rt, 0); masm.emitUnalignedLoad(isSigned, access.byteSize(), ptr.reg, scratch, rt, 0);
@ -3405,7 +3405,7 @@ class BaseCompiler
void void
storeI32(MemoryAccessDesc access, RegI32 ptr, Register rt) { storeI32(MemoryAccessDesc access, RegI32 ptr, Register rt) {
if (access.byteSize() > 1 && access.isUnaligned()) { if (access.byteSize() > 1 && IsUnaligned(ins->access())) {
masm.add32(HeapReg, ptr.reg); masm.add32(HeapReg, ptr.reg);
masm.emitUnalignedStore(access.byteSize(), ptr.reg, rt, 0); masm.emitUnalignedStore(access.byteSize(), ptr.reg, rt, 0);
} else { } else {
@ -3419,7 +3419,7 @@ class BaseCompiler
void void
loadI64(MemoryAccessDesc access, RegI32 ptr, RegI64 dest) { loadI64(MemoryAccessDesc access, RegI32 ptr, RegI64 dest) {
if (access.isUnaligned()) { if (IsUnaligned(ins->access())) {
masm.add32(HeapReg, ptr.reg); masm.add32(HeapReg, ptr.reg);
SecondScratchRegisterScope scratch(*this); SecondScratchRegisterScope scratch(*this);
masm.emitUnalignedLoad(IsSigned(false), ByteSize(4), ptr.reg, scratch, dest.reg.low, masm.emitUnalignedLoad(IsSigned(false), ByteSize(4), ptr.reg, scratch, dest.reg.low,
@ -3440,7 +3440,7 @@ class BaseCompiler
void void
storeI64(MemoryAccessDesc access, RegI32 ptr, RegI64 src) { storeI64(MemoryAccessDesc access, RegI32 ptr, RegI64 src) {
if (access.isUnaligned()) { if (IsUnaligned(ins->access())) {
masm.add32(HeapReg, ptr.reg); masm.add32(HeapReg, ptr.reg);
masm.emitUnalignedStore(ByteSize(4), ptr.reg, src.reg.low, 0); masm.emitUnalignedStore(ByteSize(4), ptr.reg, src.reg.low, 0);
masm.emitUnalignedStore(ByteSize(4), ptr.reg, src.reg.high, 4); masm.emitUnalignedStore(ByteSize(4), ptr.reg, src.reg.high, 4);
@ -3459,7 +3459,7 @@ class BaseCompiler
void void
loadF32(MemoryAccessDesc access, RegI32 ptr, RegF32 dest, RegI32 tmp1) { loadF32(MemoryAccessDesc access, RegI32 ptr, RegF32 dest, RegI32 tmp1) {
masm.add32(HeapReg, ptr.reg); masm.add32(HeapReg, ptr.reg);
if (access.isUnaligned()) { if (IsUnaligned(ins->access())) {
SecondScratchRegisterScope scratch(*this); SecondScratchRegisterScope scratch(*this);
masm.emitUnalignedLoad(IsSigned(false), ByteSize(4), ptr.reg, scratch, tmp1.reg, 0); masm.emitUnalignedLoad(IsSigned(false), ByteSize(4), ptr.reg, scratch, tmp1.reg, 0);
masm.ma_vxfer(tmp1.reg, dest.reg); masm.ma_vxfer(tmp1.reg, dest.reg);
@ -3473,7 +3473,7 @@ class BaseCompiler
void void
storeF32(MemoryAccessDesc access, RegI32 ptr, RegF32 src, RegI32 tmp1) { storeF32(MemoryAccessDesc access, RegI32 ptr, RegF32 src, RegI32 tmp1) {
masm.add32(HeapReg, ptr.reg); masm.add32(HeapReg, ptr.reg);
if (access.isUnaligned()) { if (IsUnaligned(ins->access())) {
masm.ma_vxfer(src.reg, tmp1.reg); masm.ma_vxfer(src.reg, tmp1.reg);
masm.emitUnalignedStore(ByteSize(4), ptr.reg, tmp1.reg, 0); masm.emitUnalignedStore(ByteSize(4), ptr.reg, tmp1.reg, 0);
} else { } else {
@ -3486,7 +3486,7 @@ class BaseCompiler
void void
loadF64(MemoryAccessDesc access, RegI32 ptr, RegF64 dest, RegI32 tmp1, RegI32 tmp2) { loadF64(MemoryAccessDesc access, RegI32 ptr, RegF64 dest, RegI32 tmp1, RegI32 tmp2) {
masm.add32(HeapReg, ptr.reg); masm.add32(HeapReg, ptr.reg);
if (access.isUnaligned()) { if (IsUnaligned(ins->access())) {
SecondScratchRegisterScope scratch(*this); SecondScratchRegisterScope scratch(*this);
masm.emitUnalignedLoad(IsSigned(false), ByteSize(4), ptr.reg, scratch, tmp1.reg, 0); masm.emitUnalignedLoad(IsSigned(false), ByteSize(4), ptr.reg, scratch, tmp1.reg, 0);
masm.emitUnalignedLoad(IsSigned(false), ByteSize(4), ptr.reg, scratch, tmp2.reg, 4); masm.emitUnalignedLoad(IsSigned(false), ByteSize(4), ptr.reg, scratch, tmp2.reg, 4);
@ -3501,7 +3501,7 @@ class BaseCompiler
void void
storeF64(MemoryAccessDesc access, RegI32 ptr, RegF64 src, RegI32 tmp1, RegI32 tmp2) { storeF64(MemoryAccessDesc access, RegI32 ptr, RegF64 src, RegI32 tmp1, RegI32 tmp2) {
masm.add32(HeapReg, ptr.reg); masm.add32(HeapReg, ptr.reg);
if (access.isUnaligned()) { if (IsUnaligned(ins->access())) {
masm.ma_vxfer(src.reg, tmp1.reg, tmp2.reg); masm.ma_vxfer(src.reg, tmp1.reg, tmp2.reg);
masm.emitUnalignedStore(ByteSize(4), ptr.reg, tmp1.reg, 0); masm.emitUnalignedStore(ByteSize(4), ptr.reg, tmp1.reg, 0);
masm.emitUnalignedStore(ByteSize(4), ptr.reg, tmp2.reg, 4); masm.emitUnalignedStore(ByteSize(4), ptr.reg, tmp2.reg, 4);
@ -5991,7 +5991,7 @@ BaseCompiler::emitLoad(ValType type, Scalar::Type viewType)
case ValType::I32: { case ValType::I32: {
RegI32 rp = popI32(); RegI32 rp = popI32();
#ifdef JS_CODEGEN_ARM #ifdef JS_CODEGEN_ARM
RegI32 rv = access.isUnaligned() ? needI32() : rp; RegI32 rv = IsUnaligned(access) ? needI32() : rp;
#else #else
RegI32 rv = rp; RegI32 rv = rp;
#endif #endif