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Issue #1962 - Update libtheora.
Removed some obsolete patches that were either backports from newer svn revisions, or a fix for older, non-applicable assemblers. Update our own README to account for upstream's migration to git. I didn't remove the bug 703135 patch as it's for MSVC it seems, and we still use MSVC for Windows. Also deleted some unneeded upstream code deleted by Mozilla as well.
This commit is contained in:
Job Bautista
roytam1
parent
1694b1b762
commit
be2516a091
61 changed files with 1212 additions and 2349 deletions
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@ -11,17 +11,11 @@
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;********************************************************************
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; Original implementation:
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; Copyright (C) 2009 Robin Watts for Pinknoise Productions Ltd
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; last mod: $Id: armidct.s 17481 2010-10-03 22:49:42Z tterribe $
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; last mod: $Id$
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;********************************************************************
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AREA |.text|, CODE, READONLY
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; Explicitly specifying alignment here because some versions of
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; gas don't align code correctly. See
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; http://lists.gnu.org/archive/html/bug-binutils/2011-06/msg00199.html
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; https://bugzilla.mozilla.org/show_bug.cgi?id=920992
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ALIGN
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GET armopts.s
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EXPORT oc_idct8x8_1_arm
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@ -70,11 +64,8 @@ oc_idct8x8_slow_arm
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BL idct8core_arm
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BL idct8core_arm
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LDR r0, [r13], #4 ; Write to the final destination.
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; Clear input data for next block (decoder only).
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SUB r2, r1, #8*16
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CMP r0, r2
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MOV r1, r13 ; And read from temp storage.
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BEQ oc_idct8x8_slow_arm_cols
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; Clear input data for next block.
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MOV r4, #0
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MOV r5, #0
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MOV r6, #0
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@ -87,7 +78,7 @@ oc_idct8x8_slow_arm
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STMIA r2!,{r4,r5,r6,r7}
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STMIA r2!,{r4,r5,r6,r7}
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STMIA r2!,{r4,r5,r6,r7}
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oc_idct8x8_slow_arm_cols
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MOV r1, r13 ; And read from temp storage.
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; Column transforms
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BL idct8core_down_arm
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BL idct8core_down_arm
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@ -111,18 +102,15 @@ oc_idct8x8_10_arm PROC
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BL idct3core_arm
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BL idct2core_arm
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BL idct1core_arm
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; Clear input data for next block (decoder only).
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SUB r0, r1, #4*16
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CMP r0, r2
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MOV r1, r13 ; Read from temp storage.
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BEQ oc_idct8x8_10_arm_cols
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; Clear input data for next block.
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MOV r4, #0
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STR r4, [r0]
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STR r4, [r0,#4]
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STR r4, [r0,#16]
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STR r4, [r0,#20]
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STR r4, [r0,#32]
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STR r4, [r0,#48]
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STR r4, [r1,#-4*16]!
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STR r4, [r1,#4]
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STR r4, [r1,#16]
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STR r4, [r1,#20]
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STR r4, [r1,#32]
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STR r4, [r1,#48]
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MOV r1, r13 ; Read from temp storage.
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MOV r0, r2 ; Write to the final destination
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oc_idct8x8_10_arm_cols
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; Column transforms
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@ -147,18 +135,14 @@ oc_idct8x8_6_arm PROC
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BL idct3core_arm
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BL idct2core_arm
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BL idct1core_arm
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; Clear input data for next block (decoder only).
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SUB r0, r1, #3*16
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CMP r0, r2
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MOV r1, r13 ; Read from temp storage.
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BEQ oc_idct8x8_6_arm_cols
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; Clear input data for next block.
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MOV r4, #0
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STR r4, [r0]
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STR r4, [r0,#4]
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STR r4, [r0,#16]
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STR r4, [r0,#32]
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STR r4, [r1,#-3*16]!
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STR r4, [r1,#4]
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STR r4, [r1,#16]
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STR r4, [r1,#32]
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MOV r1, r13 ; Read from temp storage.
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MOV r0, r2 ; Write to the final destination
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oc_idct8x8_6_arm_cols
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; Column transforms
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BL idct3core_down_arm
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BL idct3core_down_arm
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@ -180,14 +164,12 @@ oc_idct8x8_3_arm PROC
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MOV r0, r13 ; Write to temp storage.
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BL idct2core_arm
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BL idct1core_arm
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; Clear input data for next block (decoder only).
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SUB r0, r1, #2*16
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CMP r0, r2
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; Clear input data for next block.
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MOV r4, #0
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STR r4, [r1,#-2*16]!
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STR r4, [r1,#16]
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MOV r1, r13 ; Read from temp storage.
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MOVNE r4, #0
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STRNE r4, [r0]
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STRNE r4, [r0,#16]
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MOVNE r0, r2 ; Write to the final destination
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MOV r0, r2 ; Write to the final destination
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; Column transforms
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BL idct2core_down_arm
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BL idct2core_down_arm
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@ -805,30 +787,26 @@ oc_idct8x8_slow_v6
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BL idct8_8core_v6
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BL idct8_8core_v6
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LDR r0, [r13], #4 ; Write to the final destination.
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; Clear input data for next block (decoder only).
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SUB r2, r1, #8*16
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CMP r0, r2
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MOV r1, r13 ; And read from temp storage.
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BEQ oc_idct8x8_slow_v6_cols
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; Clear input data for next block.
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MOV r4, #0
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MOV r5, #0
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STRD r4, [r2], #8
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STRD r4, [r2], #8
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STRD r4, [r2], #8
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STRD r4, [r2], #8
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STRD r4, [r2], #8
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STRD r4, [r2], #8
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STRD r4, [r2], #8
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STRD r4, [r2], #8
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STRD r4, [r2], #8
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STRD r4, [r2], #8
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STRD r4, [r2], #8
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STRD r4, [r2], #8
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STRD r4, [r2], #8
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STRD r4, [r2], #8
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STRD r4, [r2], #8
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STRD r4, [r2], #8
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oc_idct8x8_slow_v6_cols
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STRD r4, [r1,#-8*16]!
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STRD r4, [r1,#8]
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STRD r4, [r1,#16]
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STRD r4, [r1,#24]
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STRD r4, [r1,#32]
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STRD r4, [r1,#40]
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STRD r4, [r1,#48]
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STRD r4, [r1,#56]
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STRD r4, [r1,#64]
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STRD r4, [r1,#72]
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STRD r4, [r1,#80]
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STRD r4, [r1,#88]
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STRD r4, [r1,#96]
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STRD r4, [r1,#104]
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STRD r4, [r1,#112]
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STRD r4, [r1,#120]
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MOV r1, r13 ; And read from temp storage.
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; Column transforms
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BL idct8_8core_down_v6
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BL idct8_8core_down_v6
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@ -849,20 +827,16 @@ oc_idct8x8_10_v6 PROC
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BL idct4_3core_v6
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BL idct2_1core_v6
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LDR r0, [r13], #4 ; Write to the final destination.
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; Clear input data for next block (decoder only).
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SUB r2, r1, #4*16
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CMP r0, r2
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AND r1, r13,#4 ; Align the stack.
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BEQ oc_idct8x8_10_v6_cols
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; Clear input data for next block.
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MOV r4, #0
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MOV r5, #0
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STRD r4, [r2]
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STRD r4, [r2,#16]
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STR r4, [r2,#32]
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STR r4, [r2,#48]
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oc_idct8x8_10_v6_cols
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; Column transforms
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STRD r4, [r1,#-4*16]!
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STRD r4, [r1,#16]
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STR r4, [r1,#32]
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STR r4, [r1,#48]
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AND r1, r13,#4 ; Align the stack.
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ADD r1, r1, r13 ; And read from temp storage.
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; Column transforms
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BL idct4_4core_down_v6
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BL idct4_4core_down_v6
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BL idct4_4core_down_v6
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@ -878,14 +852,12 @@ oc_idct8x8_3_v6 PROC
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MOV r8, r0
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MOV r0, r13 ; Write to temp storage.
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BL idct2_1core_v6
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; Clear input data for next block (decoder only).
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SUB r0, r1, #2*16
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CMP r0, r8
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; Clear input data for next block.
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MOV r4, #0
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STR r4, [r1,#-2*16]!
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STR r4, [r1,#16]
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MOV r1, r13 ; Read from temp storage.
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MOVNE r4, #0
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STRNE r4, [r0]
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STRNE r4, [r0,#16]
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MOVNE r0, r8 ; Write to the final destination.
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MOV r0, r8 ; Write to the final destination.
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; Column transforms
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BL idct2_2core_down_v6
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BL idct2_2core_down_v6
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@ -1041,20 +1013,16 @@ oc_idct8x8_6_v6 PROC
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ADD r0, r0, r13 ; Write to temp storage.
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BL idct3_2core_v6
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BL idct1core_v6
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; Clear input data for next block (decoder only).
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SUB r0, r1, #3*16
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CMP r0, r8
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AND r1, r13,#4 ; Align the stack.
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BEQ oc_idct8x8_6_v6_cols
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; Clear input data for next block.
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MOV r4, #0
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MOV r5, #0
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STRD r4, [r0]
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STR r4, [r0,#16]
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STR r4, [r0,#32]
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STRD r4, [r1,#-3*16]!
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STR r4, [r1,#16]
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STR r4, [r1,#32]
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AND r1, r13,#4 ; Align the stack.
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MOV r0, r8 ; Write to the final destination.
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oc_idct8x8_6_v6_cols
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; Column transforms
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ADD r1, r1, r13 ; And read from temp storage.
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; Column transforms
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BL idct3_3core_down_v6
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BL idct3_3core_down_v6
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BL idct3_3core_down_v6
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@ -1596,7 +1564,6 @@ oc_idct8x8_slow_neon
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VSWP D23,D30
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; Column transforms
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BL oc_idct8x8_stage123_neon
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CMP r0,r1
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; We have to put the return address back in the LR, or the branch
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; predictor will not recognize the function return and mis-predict the
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; entire call stack.
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@ -1610,7 +1577,6 @@ oc_idct8x8_slow_neon
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VADD.S16 Q10,Q10,Q5 ; Q10 = y[2]=t[2]'+t[5]''
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VSUB.S16 Q12,Q11,Q4 ; Q12 = y[4]=t[3]'-t[4]'
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VADD.S16 Q11,Q11,Q4 ; Q11 = y[3]=t[3]'+t[4]'
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BEQ oc_idct8x8_slow_neon_noclear
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VMOV.I8 Q2,#0
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VPOP {D8-D15}
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VMOV.I8 Q3,#0
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@ -1628,19 +1594,6 @@ oc_idct8x8_slow_neon
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VRSHR.S16 Q15,Q15,#4 ; Q15 = y[7]+8>>4
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VSTMIA r0, {D16-D31}
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MOV PC, r14
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oc_idct8x8_slow_neon_noclear
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VPOP {D8-D15}
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VRSHR.S16 Q8, Q8, #4 ; Q8 = y[0]+8>>4
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VRSHR.S16 Q9, Q9, #4 ; Q9 = y[1]+8>>4
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VRSHR.S16 Q10,Q10,#4 ; Q10 = y[2]+8>>4
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VRSHR.S16 Q11,Q11,#4 ; Q11 = y[3]+8>>4
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VRSHR.S16 Q12,Q12,#4 ; Q12 = y[4]+8>>4
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VRSHR.S16 Q13,Q13,#4 ; Q13 = y[5]+8>>4
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VRSHR.S16 Q14,Q14,#4 ; Q14 = y[6]+8>>4
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VRSHR.S16 Q15,Q15,#4 ; Q15 = y[7]+8>>4
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VSTMIA r0, {D16-D31}
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MOV PC, r14
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ENDP
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oc_idct8x8_stage123_neon PROC
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@ -1871,7 +1824,6 @@ oc_idct8x8_10_neon PROC
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VADD.S16 Q10,Q1, Q2 ; Q10= t[1]'=t[0]+t[2]
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VSUB.S16 Q2, Q1, Q2 ; Q2 = t[2]'=t[0]-t[2]
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; Stage 4
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CMP r0, r1
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VADD.S16 Q8, Q11,Q15 ; Q8 = y[0]=t[0]'+t[7]'
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VADD.S16 Q9, Q10,Q14 ; Q9 = y[1]=t[1]'+t[6]''
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VSUB.S16 Q15,Q11,Q15 ; Q15 = y[7]=t[0]'-t[7]'
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@ -1880,7 +1832,6 @@ oc_idct8x8_10_neon PROC
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VADD.S16 Q11,Q3, Q12 ; Q11 = y[3]=t[3]'+t[4]'
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VSUB.S16 Q12,Q3, Q12 ; Q12 = y[4]=t[3]'-t[4]'
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VSUB.S16 Q13,Q2, Q13 ; Q13 = y[5]=t[2]'-t[5]''
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BEQ oc_idct8x8_10_neon_noclear
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VMOV.I8 D2, #0
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VRSHR.S16 Q8, Q8, #4 ; Q8 = y[0]+8>>4
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VST1.64 {D2}, [r1@64], r12
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@ -1896,18 +1847,6 @@ oc_idct8x8_10_neon PROC
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VRSHR.S16 Q15,Q15,#4 ; Q15 = y[7]+8>>4
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VSTMIA r0, {D16-D31}
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MOV PC, r14
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oc_idct8x8_10_neon_noclear
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VRSHR.S16 Q8, Q8, #4 ; Q8 = y[0]+8>>4
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VRSHR.S16 Q9, Q9, #4 ; Q9 = y[1]+8>>4
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VRSHR.S16 Q10,Q10,#4 ; Q10 = y[2]+8>>4
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VRSHR.S16 Q11,Q11,#4 ; Q11 = y[3]+8>>4
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VRSHR.S16 Q12,Q12,#4 ; Q12 = y[4]+8>>4
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VRSHR.S16 Q13,Q13,#4 ; Q13 = y[5]+8>>4
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VRSHR.S16 Q14,Q14,#4 ; Q14 = y[6]+8>>4
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VRSHR.S16 Q15,Q15,#4 ; Q15 = y[7]+8>>4
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VSTMIA r0, {D16-D31}
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MOV PC, r14
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ENDP
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]
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