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https://repo.dactyloidae.xyz/Dactyloidae/UXP.git
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Issue #3049 - Enable loongarch64 JIT atomics
This commit is contained in:
Basilisk-Dev
wuggy
parent
bb16a45039
commit
4c58aa2724
3 changed files with 699 additions and 16 deletions
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@ -306,58 +306,307 @@ CodeGeneratorLoongArch64::visitWasmAddOffset(LWasmAddOffset* lir)
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masm.branchPtr(Assembler::Below, out, limitBase, trap(mir, wasm::Trap::OutOfBounds));
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}
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template <typename S, typename T>
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static void
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AtomicBinopToTypedIntArray(MacroAssemblerLOONGARCH64Compat& masm, AtomicOp op,
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Scalar::Type arrayType, const S& value,
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const T& mem, Register outTemp,
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Register valueTemp, Register offsetTemp,
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Register maskTemp, AnyRegister output)
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{
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switch (arrayType) {
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case Scalar::Int8:
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masm.atomicFetchOp(1, true, op, value, mem, valueTemp, offsetTemp,
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maskTemp, output.gpr());
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break;
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case Scalar::Uint8:
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masm.atomicFetchOp(1, false, op, value, mem, valueTemp, offsetTemp,
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maskTemp, output.gpr());
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break;
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case Scalar::Int16:
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masm.atomicFetchOp(2, true, op, value, mem, valueTemp, offsetTemp,
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maskTemp, output.gpr());
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break;
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case Scalar::Uint16:
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masm.atomicFetchOp(2, false, op, value, mem, valueTemp, offsetTemp,
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maskTemp, output.gpr());
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break;
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case Scalar::Int32:
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masm.atomicFetchOp(4, false, op, value, mem, valueTemp, offsetTemp,
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maskTemp, output.gpr());
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break;
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case Scalar::Uint32:
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MOZ_ASSERT(output.isFloat());
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MOZ_ASSERT(outTemp != InvalidReg);
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masm.atomicFetchOp(4, false, op, value, mem, valueTemp, offsetTemp,
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maskTemp, outTemp);
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masm.convertUInt32ToDouble(outTemp, output.fpu());
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break;
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default:
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MOZ_CRASH("Invalid typed array type");
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}
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}
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template <typename S, typename T>
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static void
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AtomicBinopToTypedIntArray(MacroAssemblerLOONGARCH64Compat& masm, AtomicOp op,
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Scalar::Type arrayType, const S& value,
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const T& mem, Register valueTemp,
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Register offsetTemp, Register maskTemp)
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{
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switch (arrayType) {
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case Scalar::Int8:
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case Scalar::Uint8:
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masm.atomicEffectOp(1, op, value, mem, valueTemp, offsetTemp,
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maskTemp);
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break;
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case Scalar::Int16:
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case Scalar::Uint16:
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masm.atomicEffectOp(2, op, value, mem, valueTemp, offsetTemp,
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maskTemp);
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break;
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case Scalar::Int32:
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case Scalar::Uint32:
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masm.atomicEffectOp(4, op, value, mem, valueTemp, offsetTemp,
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maskTemp);
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break;
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default:
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MOZ_CRASH("Invalid typed array type");
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}
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}
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template <typename T>
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static void
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AtomicBinopToTypedArray(MacroAssemblerLOONGARCH64Compat& masm, AtomicOp op,
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Scalar::Type arrayType, const LAllocation* value,
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const T& mem, Register outTemp, Register valueTemp,
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Register offsetTemp, Register maskTemp,
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AnyRegister output)
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{
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if (value->isConstant()) {
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AtomicBinopToTypedIntArray(masm, op, arrayType, Imm32(ToInt32(value)),
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mem, outTemp, valueTemp, offsetTemp,
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maskTemp, output);
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} else {
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AtomicBinopToTypedIntArray(masm, op, arrayType, ToRegister(value),
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mem, outTemp, valueTemp, offsetTemp,
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maskTemp, output);
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}
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}
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template <typename T>
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static void
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AtomicBinopToTypedArray(MacroAssemblerLOONGARCH64Compat& masm, AtomicOp op,
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Scalar::Type arrayType, const LAllocation* value,
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const T& mem, Register valueTemp, Register offsetTemp,
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Register maskTemp)
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{
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if (value->isConstant()) {
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AtomicBinopToTypedIntArray(masm, op, arrayType, Imm32(ToInt32(value)),
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mem, valueTemp, offsetTemp, maskTemp);
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} else {
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AtomicBinopToTypedIntArray(masm, op, arrayType, ToRegister(value),
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mem, valueTemp, offsetTemp, maskTemp);
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}
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}
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void
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CodeGeneratorLoongArch64::visitAsmJSCompareExchangeHeap(LAsmJSCompareExchangeHeap* ins)
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{
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(void)ins;
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MOZ_CRASH("asm.js atomics are not supported on loongarch64 yet");
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MAsmJSCompareExchangeHeap* mir = ins->mir();
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Scalar::Type vt = mir->access().type();
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Register ptrReg = ToRegister(ins->ptr());
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BaseIndex srcAddr(HeapReg, ptrReg, TimesOne);
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MOZ_ASSERT(ins->addrTemp()->isBogusTemp());
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Register oldval = ToRegister(ins->oldValue());
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Register newval = ToRegister(ins->newValue());
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Register valueTemp = ToRegister(ins->valueTemp());
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Register offsetTemp = ToRegister(ins->offsetTemp());
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Register maskTemp = ToRegister(ins->maskTemp());
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masm.compareExchangeToTypedIntArray(
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vt == Scalar::Uint32 ? Scalar::Int32 : vt, srcAddr, oldval, newval,
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InvalidReg, valueTemp, offsetTemp, maskTemp,
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ToAnyRegister(ins->output()));
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}
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void
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CodeGeneratorLoongArch64::visitAsmJSAtomicExchangeHeap(LAsmJSAtomicExchangeHeap* ins)
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{
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(void)ins;
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MOZ_CRASH("asm.js atomics are not supported on loongarch64 yet");
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MAsmJSAtomicExchangeHeap* mir = ins->mir();
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Scalar::Type vt = mir->access().type();
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Register ptrReg = ToRegister(ins->ptr());
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Register value = ToRegister(ins->value());
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BaseIndex srcAddr(HeapReg, ptrReg, TimesOne);
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MOZ_ASSERT(ins->addrTemp()->isBogusTemp());
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Register valueTemp = ToRegister(ins->valueTemp());
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Register offsetTemp = ToRegister(ins->offsetTemp());
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Register maskTemp = ToRegister(ins->maskTemp());
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masm.atomicExchangeToTypedIntArray(
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vt == Scalar::Uint32 ? Scalar::Int32 : vt, srcAddr, value, InvalidReg,
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valueTemp, offsetTemp, maskTemp, ToAnyRegister(ins->output()));
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}
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void
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CodeGeneratorLoongArch64::visitAsmJSAtomicBinopHeap(LAsmJSAtomicBinopHeap* ins)
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{
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(void)ins;
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MOZ_CRASH("asm.js atomics are not supported on loongarch64 yet");
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MOZ_ASSERT(ins->mir()->hasUses());
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MOZ_ASSERT(ins->addrTemp()->isBogusTemp());
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MAsmJSAtomicBinopHeap* mir = ins->mir();
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Scalar::Type vt = mir->access().type();
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Register ptrReg = ToRegister(ins->ptr());
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Register valueTemp = ToRegister(ins->valueTemp());
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Register offsetTemp = ToRegister(ins->offsetTemp());
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Register maskTemp = ToRegister(ins->maskTemp());
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const LAllocation* value = ins->value();
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AtomicOp op = mir->operation();
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BaseIndex srcAddr(HeapReg, ptrReg, TimesOne);
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AtomicBinopToTypedArray(masm, op,
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vt == Scalar::Uint32 ? Scalar::Int32 : vt, value,
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srcAddr, InvalidReg, valueTemp, offsetTemp,
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maskTemp, ToAnyRegister(ins->output()));
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}
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void
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CodeGeneratorLoongArch64::visitAsmJSAtomicBinopHeapForEffect(LAsmJSAtomicBinopHeapForEffect* ins)
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{
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(void)ins;
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MOZ_CRASH("asm.js atomics are not supported on loongarch64 yet");
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MOZ_ASSERT(!ins->mir()->hasUses());
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MOZ_ASSERT(ins->addrTemp()->isBogusTemp());
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MAsmJSAtomicBinopHeap* mir = ins->mir();
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Scalar::Type vt = mir->access().type();
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Register ptrReg = ToRegister(ins->ptr());
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Register valueTemp = ToRegister(ins->valueTemp());
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Register offsetTemp = ToRegister(ins->offsetTemp());
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Register maskTemp = ToRegister(ins->maskTemp());
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const LAllocation* value = ins->value();
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AtomicOp op = mir->operation();
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BaseIndex srcAddr(HeapReg, ptrReg, TimesOne);
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AtomicBinopToTypedArray(masm, op, vt, value, srcAddr, valueTemp,
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offsetTemp, maskTemp);
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}
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void
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CodeGeneratorLoongArch64::visitAtomicTypedArrayElementBinop(LAtomicTypedArrayElementBinop* lir)
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{
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(void)lir;
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MOZ_CRASH("atomics are not supported on loongarch64 Ion yet");
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MOZ_ASSERT(lir->mir()->hasUses());
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AnyRegister output = ToAnyRegister(lir->output());
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Register elements = ToRegister(lir->elements());
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Register outTemp = lir->temp2()->isBogusTemp() ? InvalidReg
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: ToRegister(lir->temp2());
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Register valueTemp = ToRegister(lir->valueTemp());
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Register offsetTemp = ToRegister(lir->offsetTemp());
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Register maskTemp = ToRegister(lir->maskTemp());
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const LAllocation* value = lir->value();
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Scalar::Type arrayType = lir->mir()->arrayType();
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int width = Scalar::byteSize(arrayType);
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if (lir->index()->isConstant()) {
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Address mem(elements, ToInt32(lir->index()) * width);
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AtomicBinopToTypedArray(masm, lir->mir()->operation(), arrayType, value,
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mem, outTemp, valueTemp, offsetTemp, maskTemp,
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output);
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} else {
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BaseIndex mem(elements, ToRegister(lir->index()),
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ScaleFromElemWidth(width));
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AtomicBinopToTypedArray(masm, lir->mir()->operation(), arrayType, value,
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mem, outTemp, valueTemp, offsetTemp, maskTemp,
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output);
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}
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}
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void
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CodeGeneratorLoongArch64::visitAtomicTypedArrayElementBinopForEffect(LAtomicTypedArrayElementBinopForEffect* lir)
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{
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(void)lir;
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MOZ_CRASH("atomics are not supported on loongarch64 Ion yet");
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MOZ_ASSERT(!lir->mir()->hasUses());
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Register elements = ToRegister(lir->elements());
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Register valueTemp = ToRegister(lir->valueTemp());
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Register offsetTemp = ToRegister(lir->offsetTemp());
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Register maskTemp = ToRegister(lir->maskTemp());
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const LAllocation* value = lir->value();
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Scalar::Type arrayType = lir->mir()->arrayType();
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int width = Scalar::byteSize(arrayType);
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if (lir->index()->isConstant()) {
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Address mem(elements, ToInt32(lir->index()) * width);
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AtomicBinopToTypedArray(masm, lir->mir()->operation(), arrayType, value,
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mem, valueTemp, offsetTemp, maskTemp);
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} else {
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BaseIndex mem(elements, ToRegister(lir->index()),
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ScaleFromElemWidth(width));
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AtomicBinopToTypedArray(masm, lir->mir()->operation(), arrayType, value,
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mem, valueTemp, offsetTemp, maskTemp);
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}
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}
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void
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CodeGeneratorLoongArch64::visitCompareExchangeTypedArrayElement(LCompareExchangeTypedArrayElement* lir)
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{
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(void)lir;
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MOZ_CRASH("atomics are not supported on loongarch64 Ion yet");
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Register elements = ToRegister(lir->elements());
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AnyRegister output = ToAnyRegister(lir->output());
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Register temp = lir->temp()->isBogusTemp() ? InvalidReg
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: ToRegister(lir->temp());
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Register oldval = ToRegister(lir->oldval());
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Register newval = ToRegister(lir->newval());
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Register valueTemp = ToRegister(lir->valueTemp());
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Register offsetTemp = ToRegister(lir->offsetTemp());
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Register maskTemp = ToRegister(lir->maskTemp());
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Scalar::Type arrayType = lir->mir()->arrayType();
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int width = Scalar::byteSize(arrayType);
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if (lir->index()->isConstant()) {
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Address dest(elements, ToInt32(lir->index()) * width);
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masm.compareExchangeToTypedIntArray(arrayType, dest, oldval, newval,
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temp, valueTemp, offsetTemp,
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maskTemp, output);
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} else {
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BaseIndex dest(elements, ToRegister(lir->index()),
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ScaleFromElemWidth(width));
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masm.compareExchangeToTypedIntArray(arrayType, dest, oldval, newval,
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temp, valueTemp, offsetTemp,
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maskTemp, output);
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}
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}
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void
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CodeGeneratorLoongArch64::visitAtomicExchangeTypedArrayElement(LAtomicExchangeTypedArrayElement* lir)
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{
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(void)lir;
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MOZ_CRASH("atomics are not supported on loongarch64 Ion yet");
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Register elements = ToRegister(lir->elements());
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AnyRegister output = ToAnyRegister(lir->output());
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Register temp = lir->temp()->isBogusTemp() ? InvalidReg
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: ToRegister(lir->temp());
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Register value = ToRegister(lir->value());
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Register valueTemp = ToRegister(lir->valueTemp());
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Register offsetTemp = ToRegister(lir->offsetTemp());
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Register maskTemp = ToRegister(lir->maskTemp());
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Scalar::Type arrayType = lir->mir()->arrayType();
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int width = Scalar::byteSize(arrayType);
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if (lir->index()->isConstant()) {
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Address dest(elements, ToInt32(lir->index()) * width);
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masm.atomicExchangeToTypedIntArray(arrayType, dest, value, temp,
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valueTemp, offsetTemp, maskTemp,
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output);
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} else {
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BaseIndex dest(elements, ToRegister(lir->index()),
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ScaleFromElemWidth(width));
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masm.atomicExchangeToTypedIntArray(arrayType, dest, value, temp,
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valueTemp, offsetTemp, maskTemp,
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output);
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}
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}
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@ -22,6 +22,140 @@
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namespace js {
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namespace jit {
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namespace {
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static inline void MoveAtomicValue(MacroAssemblerLOONGARCH64Compat& masm,
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Imm32 value, Register dest) {
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masm.move32(value, dest);
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}
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static inline void MoveAtomicValue(MacroAssemblerLOONGARCH64Compat& masm,
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Register value, Register dest) {
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masm.move32(value, dest);
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}
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static inline void SignExtendAtomicResult(MacroAssemblerLOONGARCH64Compat& masm,
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int nbytes, Register output) {
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switch (nbytes) {
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case 1:
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masm.as_ext_w_b(output, output);
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break;
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case 2:
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masm.as_ext_w_h(output, output);
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break;
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case 4:
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break;
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default:
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MOZ_CRASH("unexpected atomic width");
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}
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}
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template <typename T>
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static inline void PrepareAtomicAddress(
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MacroAssemblerLOONGARCH64Compat& masm, int nbytes, const T& address,
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Register offsetTemp, Register maskTemp) {
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masm.computeEffectiveAddress(address, ScratchRegister);
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masm.as_andi(offsetTemp, ScratchRegister, 3);
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masm.as_sub_d(ScratchRegister, ScratchRegister, offsetTemp);
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masm.as_slli_w(offsetTemp, offsetTemp, 3);
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masm.ma_li(maskTemp, Imm32(int32_t(UINT32_MAX >> ((4 - nbytes) * 8))));
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masm.as_sll_w(maskTemp, maskTemp, offsetTemp);
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}
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template <typename S, typename T>
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static void AtomicFetchOpLoongArch64(MacroAssemblerLOONGARCH64Compat& masm,
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int nbytes, bool signExtend, AtomicOp op,
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const S& value, const T& address,
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Register valueTemp, Register offsetTemp,
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Register maskTemp, Register output) {
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Label again;
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PrepareAtomicAddress(masm, nbytes, address, offsetTemp, maskTemp);
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masm.bind(&again);
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masm.as_dbar(0);
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masm.as_ll_w(SecondScratchReg, ScratchRegister, 0);
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if (output != InvalidReg) {
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masm.as_and(output, SecondScratchReg, maskTemp);
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masm.as_srl_w(output, output, offsetTemp);
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if (signExtend) {
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SignExtendAtomicResult(masm, nbytes, output);
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}
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}
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MoveAtomicValue(masm, value, valueTemp);
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masm.as_sll_w(valueTemp, valueTemp, offsetTemp);
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switch (op) {
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case AtomicFetchAddOp:
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masm.as_add_w(valueTemp, SecondScratchReg, valueTemp);
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break;
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case AtomicFetchSubOp:
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masm.as_sub_w(valueTemp, SecondScratchReg, valueTemp);
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break;
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case AtomicFetchAndOp:
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masm.as_and(valueTemp, SecondScratchReg, valueTemp);
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break;
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case AtomicFetchOrOp:
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masm.as_or(valueTemp, SecondScratchReg, valueTemp);
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break;
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case AtomicFetchXorOp:
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masm.as_xor(valueTemp, SecondScratchReg, valueTemp);
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break;
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default:
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MOZ_CRASH("unexpected atomic op");
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}
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masm.as_and(valueTemp, valueTemp, maskTemp);
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masm.as_or(SecondScratchReg, SecondScratchReg, maskTemp);
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masm.as_xor(SecondScratchReg, SecondScratchReg, maskTemp);
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masm.as_or(SecondScratchReg, SecondScratchReg, valueTemp);
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masm.as_sc_w(SecondScratchReg, ScratchRegister, 0);
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masm.ma_b(SecondScratchReg, SecondScratchReg, &again, Assembler::Zero,
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ShortJump);
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masm.as_dbar(0);
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}
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template <typename T>
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static void CompareExchangeLoongArch64(
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MacroAssemblerLOONGARCH64Compat& masm, int nbytes, bool signExtend,
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const T& address, Register oldval, Register newval, Register valueTemp,
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Register offsetTemp, Register maskTemp, Register output) {
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Label again, done;
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PrepareAtomicAddress(masm, nbytes, address, offsetTemp, maskTemp);
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masm.bind(&again);
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masm.as_dbar(0);
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masm.as_ll_w(SecondScratchReg, ScratchRegister, 0);
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masm.as_and(output, SecondScratchReg, maskTemp);
|
||||
masm.as_srl_w(output, output, offsetTemp);
|
||||
if (signExtend) {
|
||||
SignExtendAtomicResult(masm, nbytes, output);
|
||||
}
|
||||
|
||||
if (oldval != InvalidReg) {
|
||||
masm.ma_b(output, oldval, &done, Assembler::NotEqual, ShortJump);
|
||||
}
|
||||
|
||||
masm.move32(newval, valueTemp);
|
||||
masm.as_sll_w(valueTemp, valueTemp, offsetTemp);
|
||||
masm.as_and(valueTemp, valueTemp, maskTemp);
|
||||
masm.as_or(SecondScratchReg, SecondScratchReg, maskTemp);
|
||||
masm.as_xor(SecondScratchReg, SecondScratchReg, maskTemp);
|
||||
masm.as_or(SecondScratchReg, SecondScratchReg, valueTemp);
|
||||
masm.as_sc_w(SecondScratchReg, ScratchRegister, 0);
|
||||
masm.ma_b(SecondScratchReg, SecondScratchReg, &again, Assembler::Zero,
|
||||
ShortJump);
|
||||
masm.as_dbar(0);
|
||||
|
||||
masm.bind(&done);
|
||||
}
|
||||
|
||||
} // namespace
|
||||
|
||||
void MacroAssembler::alignFrameForICArguments(AfterICSaveLive& aic) {
|
||||
if (framePushed() % ABIStackAlignment != 0) {
|
||||
aic.alignmentPadding = ABIStackAlignment - (framePushed() % ABIStackAlignment);
|
||||
|
|
@ -3244,6 +3378,246 @@ void MacroAssemblerLOONGARCH64Compat::storePtr(Register src, AbsoluteAddress des
|
|||
storePtr(src, Address(scratch, 0));
|
||||
}
|
||||
|
||||
void MacroAssemblerLOONGARCH64Compat::atomicEffectOp(
|
||||
int nbytes, AtomicOp op, Imm32 value, const Address& address,
|
||||
Register valueTemp, Register offsetTemp, Register maskTemp) {
|
||||
AtomicFetchOpLoongArch64(*this, nbytes, false, op, value, address, valueTemp,
|
||||
offsetTemp, maskTemp, InvalidReg);
|
||||
}
|
||||
|
||||
void MacroAssemblerLOONGARCH64Compat::atomicEffectOp(
|
||||
int nbytes, AtomicOp op, Imm32 value, const BaseIndex& address,
|
||||
Register valueTemp, Register offsetTemp, Register maskTemp) {
|
||||
AtomicFetchOpLoongArch64(*this, nbytes, false, op, value, address, valueTemp,
|
||||
offsetTemp, maskTemp, InvalidReg);
|
||||
}
|
||||
|
||||
void MacroAssemblerLOONGARCH64Compat::atomicEffectOp(
|
||||
int nbytes, AtomicOp op, Register value, const Address& address,
|
||||
Register valueTemp, Register offsetTemp, Register maskTemp) {
|
||||
AtomicFetchOpLoongArch64(*this, nbytes, false, op, value, address, valueTemp,
|
||||
offsetTemp, maskTemp, InvalidReg);
|
||||
}
|
||||
|
||||
void MacroAssemblerLOONGARCH64Compat::atomicEffectOp(
|
||||
int nbytes, AtomicOp op, Register value, const BaseIndex& address,
|
||||
Register valueTemp, Register offsetTemp, Register maskTemp) {
|
||||
AtomicFetchOpLoongArch64(*this, nbytes, false, op, value, address, valueTemp,
|
||||
offsetTemp, maskTemp, InvalidReg);
|
||||
}
|
||||
|
||||
void MacroAssemblerLOONGARCH64Compat::atomicFetchOp(
|
||||
int nbytes, bool signExtend, AtomicOp op, Imm32 value,
|
||||
const Address& address, Register valueTemp, Register offsetTemp,
|
||||
Register maskTemp, Register output) {
|
||||
AtomicFetchOpLoongArch64(*this, nbytes, signExtend, op, value, address,
|
||||
valueTemp, offsetTemp, maskTemp, output);
|
||||
}
|
||||
|
||||
void MacroAssemblerLOONGARCH64Compat::atomicFetchOp(
|
||||
int nbytes, bool signExtend, AtomicOp op, Imm32 value,
|
||||
const BaseIndex& address, Register valueTemp, Register offsetTemp,
|
||||
Register maskTemp, Register output) {
|
||||
AtomicFetchOpLoongArch64(*this, nbytes, signExtend, op, value, address,
|
||||
valueTemp, offsetTemp, maskTemp, output);
|
||||
}
|
||||
|
||||
void MacroAssemblerLOONGARCH64Compat::atomicFetchOp(
|
||||
int nbytes, bool signExtend, AtomicOp op, Register value,
|
||||
const Address& address, Register valueTemp, Register offsetTemp,
|
||||
Register maskTemp, Register output) {
|
||||
AtomicFetchOpLoongArch64(*this, nbytes, signExtend, op, value, address,
|
||||
valueTemp, offsetTemp, maskTemp, output);
|
||||
}
|
||||
|
||||
void MacroAssemblerLOONGARCH64Compat::atomicFetchOp(
|
||||
int nbytes, bool signExtend, AtomicOp op, Register value,
|
||||
const BaseIndex& address, Register valueTemp, Register offsetTemp,
|
||||
Register maskTemp, Register output) {
|
||||
AtomicFetchOpLoongArch64(*this, nbytes, signExtend, op, value, address,
|
||||
valueTemp, offsetTemp, maskTemp, output);
|
||||
}
|
||||
|
||||
void MacroAssemblerLOONGARCH64Compat::compareExchange(
|
||||
int nbytes, bool signExtend, const Address& address, Register oldval,
|
||||
Register newval, Register valueTemp, Register offsetTemp,
|
||||
Register maskTemp, Register output) {
|
||||
CompareExchangeLoongArch64(*this, nbytes, signExtend, address, oldval,
|
||||
newval, valueTemp, offsetTemp, maskTemp, output);
|
||||
}
|
||||
|
||||
void MacroAssemblerLOONGARCH64Compat::compareExchange(
|
||||
int nbytes, bool signExtend, const BaseIndex& address, Register oldval,
|
||||
Register newval, Register valueTemp, Register offsetTemp,
|
||||
Register maskTemp, Register output) {
|
||||
CompareExchangeLoongArch64(*this, nbytes, signExtend, address, oldval,
|
||||
newval, valueTemp, offsetTemp, maskTemp, output);
|
||||
}
|
||||
|
||||
void MacroAssemblerLOONGARCH64Compat::compareExchangeToTypedIntArray(
|
||||
Scalar::Type arrayType, const Address& mem, Register oldval,
|
||||
Register newval, Register temp, Register valueTemp, Register offsetTemp,
|
||||
Register maskTemp, AnyRegister output) {
|
||||
switch (arrayType) {
|
||||
case Scalar::Int8:
|
||||
compareExchange(1, true, mem, oldval, newval, valueTemp, offsetTemp,
|
||||
maskTemp, output.gpr());
|
||||
break;
|
||||
case Scalar::Uint8:
|
||||
compareExchange(1, false, mem, oldval, newval, valueTemp, offsetTemp,
|
||||
maskTemp, output.gpr());
|
||||
break;
|
||||
case Scalar::Int16:
|
||||
compareExchange(2, true, mem, oldval, newval, valueTemp, offsetTemp,
|
||||
maskTemp, output.gpr());
|
||||
break;
|
||||
case Scalar::Uint16:
|
||||
compareExchange(2, false, mem, oldval, newval, valueTemp, offsetTemp,
|
||||
maskTemp, output.gpr());
|
||||
break;
|
||||
case Scalar::Int32:
|
||||
compareExchange(4, false, mem, oldval, newval, valueTemp, offsetTemp,
|
||||
maskTemp, output.gpr());
|
||||
break;
|
||||
case Scalar::Uint32:
|
||||
MOZ_ASSERT(output.isFloat());
|
||||
MOZ_ASSERT(temp != InvalidReg);
|
||||
compareExchange(4, false, mem, oldval, newval, valueTemp, offsetTemp,
|
||||
maskTemp, temp);
|
||||
convertUInt32ToDouble(temp, output.fpu());
|
||||
break;
|
||||
default:
|
||||
MOZ_CRASH("Invalid typed array type");
|
||||
}
|
||||
}
|
||||
|
||||
void MacroAssemblerLOONGARCH64Compat::compareExchangeToTypedIntArray(
|
||||
Scalar::Type arrayType, const BaseIndex& mem, Register oldval,
|
||||
Register newval, Register temp, Register valueTemp, Register offsetTemp,
|
||||
Register maskTemp, AnyRegister output) {
|
||||
switch (arrayType) {
|
||||
case Scalar::Int8:
|
||||
compareExchange(1, true, mem, oldval, newval, valueTemp, offsetTemp,
|
||||
maskTemp, output.gpr());
|
||||
break;
|
||||
case Scalar::Uint8:
|
||||
compareExchange(1, false, mem, oldval, newval, valueTemp, offsetTemp,
|
||||
maskTemp, output.gpr());
|
||||
break;
|
||||
case Scalar::Int16:
|
||||
compareExchange(2, true, mem, oldval, newval, valueTemp, offsetTemp,
|
||||
maskTemp, output.gpr());
|
||||
break;
|
||||
case Scalar::Uint16:
|
||||
compareExchange(2, false, mem, oldval, newval, valueTemp, offsetTemp,
|
||||
maskTemp, output.gpr());
|
||||
break;
|
||||
case Scalar::Int32:
|
||||
compareExchange(4, false, mem, oldval, newval, valueTemp, offsetTemp,
|
||||
maskTemp, output.gpr());
|
||||
break;
|
||||
case Scalar::Uint32:
|
||||
MOZ_ASSERT(output.isFloat());
|
||||
MOZ_ASSERT(temp != InvalidReg);
|
||||
compareExchange(4, false, mem, oldval, newval, valueTemp, offsetTemp,
|
||||
maskTemp, temp);
|
||||
convertUInt32ToDouble(temp, output.fpu());
|
||||
break;
|
||||
default:
|
||||
MOZ_CRASH("Invalid typed array type");
|
||||
}
|
||||
}
|
||||
|
||||
void MacroAssemblerLOONGARCH64Compat::atomicExchange(
|
||||
int nbytes, bool signExtend, const Address& address, Register value,
|
||||
Register valueTemp, Register offsetTemp, Register maskTemp,
|
||||
Register output) {
|
||||
CompareExchangeLoongArch64(*this, nbytes, signExtend, address, InvalidReg,
|
||||
value, valueTemp, offsetTemp, maskTemp, output);
|
||||
}
|
||||
|
||||
void MacroAssemblerLOONGARCH64Compat::atomicExchange(
|
||||
int nbytes, bool signExtend, const BaseIndex& address, Register value,
|
||||
Register valueTemp, Register offsetTemp, Register maskTemp,
|
||||
Register output) {
|
||||
CompareExchangeLoongArch64(*this, nbytes, signExtend, address, InvalidReg,
|
||||
value, valueTemp, offsetTemp, maskTemp, output);
|
||||
}
|
||||
|
||||
void MacroAssemblerLOONGARCH64Compat::atomicExchangeToTypedIntArray(
|
||||
Scalar::Type arrayType, const Address& mem, Register value, Register temp,
|
||||
Register valueTemp, Register offsetTemp, Register maskTemp,
|
||||
AnyRegister output) {
|
||||
switch (arrayType) {
|
||||
case Scalar::Int8:
|
||||
atomicExchange(1, true, mem, value, valueTemp, offsetTemp, maskTemp,
|
||||
output.gpr());
|
||||
break;
|
||||
case Scalar::Uint8:
|
||||
atomicExchange(1, false, mem, value, valueTemp, offsetTemp, maskTemp,
|
||||
output.gpr());
|
||||
break;
|
||||
case Scalar::Int16:
|
||||
atomicExchange(2, true, mem, value, valueTemp, offsetTemp, maskTemp,
|
||||
output.gpr());
|
||||
break;
|
||||
case Scalar::Uint16:
|
||||
atomicExchange(2, false, mem, value, valueTemp, offsetTemp, maskTemp,
|
||||
output.gpr());
|
||||
break;
|
||||
case Scalar::Int32:
|
||||
atomicExchange(4, false, mem, value, valueTemp, offsetTemp, maskTemp,
|
||||
output.gpr());
|
||||
break;
|
||||
case Scalar::Uint32:
|
||||
MOZ_ASSERT(output.isFloat());
|
||||
MOZ_ASSERT(temp != InvalidReg);
|
||||
atomicExchange(4, false, mem, value, valueTemp, offsetTemp, maskTemp,
|
||||
temp);
|
||||
convertUInt32ToDouble(temp, output.fpu());
|
||||
break;
|
||||
default:
|
||||
MOZ_CRASH("Invalid typed array type");
|
||||
}
|
||||
}
|
||||
|
||||
void MacroAssemblerLOONGARCH64Compat::atomicExchangeToTypedIntArray(
|
||||
Scalar::Type arrayType, const BaseIndex& mem, Register value,
|
||||
Register temp, Register valueTemp, Register offsetTemp,
|
||||
Register maskTemp, AnyRegister output) {
|
||||
switch (arrayType) {
|
||||
case Scalar::Int8:
|
||||
atomicExchange(1, true, mem, value, valueTemp, offsetTemp, maskTemp,
|
||||
output.gpr());
|
||||
break;
|
||||
case Scalar::Uint8:
|
||||
atomicExchange(1, false, mem, value, valueTemp, offsetTemp, maskTemp,
|
||||
output.gpr());
|
||||
break;
|
||||
case Scalar::Int16:
|
||||
atomicExchange(2, true, mem, value, valueTemp, offsetTemp, maskTemp,
|
||||
output.gpr());
|
||||
break;
|
||||
case Scalar::Uint16:
|
||||
atomicExchange(2, false, mem, value, valueTemp, offsetTemp, maskTemp,
|
||||
output.gpr());
|
||||
break;
|
||||
case Scalar::Int32:
|
||||
atomicExchange(4, false, mem, value, valueTemp, offsetTemp, maskTemp,
|
||||
output.gpr());
|
||||
break;
|
||||
case Scalar::Uint32:
|
||||
MOZ_ASSERT(output.isFloat());
|
||||
MOZ_ASSERT(temp != InvalidReg);
|
||||
atomicExchange(4, false, mem, value, valueTemp, offsetTemp, maskTemp,
|
||||
temp);
|
||||
convertUInt32ToDouble(temp, output.fpu());
|
||||
break;
|
||||
default:
|
||||
MOZ_CRASH("Invalid typed array type");
|
||||
}
|
||||
}
|
||||
|
||||
void MacroAssemblerLOONGARCH64Compat::testNullSet(Condition cond,
|
||||
const ValueOperand& value,
|
||||
Register dest) {
|
||||
|
|
|
|||
|
|
@ -1272,6 +1272,66 @@ class MacroAssemblerLOONGARCH64Compat : public MacroAssemblerLOONGARCH64 {
|
|||
void storePtr(Register src, const BaseIndex& address);
|
||||
void storePtr(Register src, AbsoluteAddress dest);
|
||||
|
||||
void atomicEffectOp(int nbytes, AtomicOp op, Imm32 value,
|
||||
const Address& address, Register valueTemp,
|
||||
Register offsetTemp, Register maskTemp);
|
||||
void atomicEffectOp(int nbytes, AtomicOp op, Imm32 value,
|
||||
const BaseIndex& address, Register valueTemp,
|
||||
Register offsetTemp, Register maskTemp);
|
||||
void atomicEffectOp(int nbytes, AtomicOp op, Register value,
|
||||
const Address& address, Register valueTemp,
|
||||
Register offsetTemp, Register maskTemp);
|
||||
void atomicEffectOp(int nbytes, AtomicOp op, Register value,
|
||||
const BaseIndex& address, Register valueTemp,
|
||||
Register offsetTemp, Register maskTemp);
|
||||
|
||||
void atomicFetchOp(int nbytes, bool signExtend, AtomicOp op, Imm32 value,
|
||||
const Address& address, Register valueTemp,
|
||||
Register offsetTemp, Register maskTemp, Register output);
|
||||
void atomicFetchOp(int nbytes, bool signExtend, AtomicOp op, Imm32 value,
|
||||
const BaseIndex& address, Register valueTemp,
|
||||
Register offsetTemp, Register maskTemp, Register output);
|
||||
void atomicFetchOp(int nbytes, bool signExtend, AtomicOp op, Register value,
|
||||
const Address& address, Register valueTemp,
|
||||
Register offsetTemp, Register maskTemp, Register output);
|
||||
void atomicFetchOp(int nbytes, bool signExtend, AtomicOp op, Register value,
|
||||
const BaseIndex& address, Register valueTemp,
|
||||
Register offsetTemp, Register maskTemp, Register output);
|
||||
|
||||
void compareExchange(int nbytes, bool signExtend, const Address& address,
|
||||
Register oldval, Register newval, Register valueTemp,
|
||||
Register offsetTemp, Register maskTemp, Register output);
|
||||
void compareExchange(int nbytes, bool signExtend, const BaseIndex& address,
|
||||
Register oldval, Register newval, Register valueTemp,
|
||||
Register offsetTemp, Register maskTemp, Register output);
|
||||
void compareExchangeToTypedIntArray(Scalar::Type arrayType,
|
||||
const Address& mem, Register oldval,
|
||||
Register newval, Register temp,
|
||||
Register valueTemp, Register offsetTemp,
|
||||
Register maskTemp, AnyRegister output);
|
||||
void compareExchangeToTypedIntArray(Scalar::Type arrayType,
|
||||
const BaseIndex& mem, Register oldval,
|
||||
Register newval, Register temp,
|
||||
Register valueTemp, Register offsetTemp,
|
||||
Register maskTemp, AnyRegister output);
|
||||
|
||||
void atomicExchange(int nbytes, bool signExtend, const Address& address,
|
||||
Register value, Register valueTemp, Register offsetTemp,
|
||||
Register maskTemp, Register output);
|
||||
void atomicExchange(int nbytes, bool signExtend, const BaseIndex& address,
|
||||
Register value, Register valueTemp, Register offsetTemp,
|
||||
Register maskTemp, Register output);
|
||||
void atomicExchangeToTypedIntArray(Scalar::Type arrayType,
|
||||
const Address& mem, Register value,
|
||||
Register temp, Register valueTemp,
|
||||
Register offsetTemp, Register maskTemp,
|
||||
AnyRegister output);
|
||||
void atomicExchangeToTypedIntArray(Scalar::Type arrayType,
|
||||
const BaseIndex& mem, Register value,
|
||||
Register temp, Register valueTemp,
|
||||
Register offsetTemp, Register maskTemp,
|
||||
AnyRegister output);
|
||||
|
||||
void moveDouble(FloatRegister src, FloatRegister dest) {
|
||||
as_fmov_d(dest, src);
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue