mirror of
https://repo.dactyloidae.xyz/Dactyloidae/UXP.git
synced 2026-10-24 16:17:29 +09:00
Update libaom to rev b25610052a1398032320008d69b51d2da94f5928
This commit is contained in:
parent
8493557d20
commit
3d109dd4fc
240 changed files with 16977 additions and 6139 deletions
84
third_party/aom/av1/common/arm/mem_neon.h
vendored
84
third_party/aom/av1/common/arm/mem_neon.h
vendored
|
|
@ -22,6 +22,14 @@ static INLINE void store_row2_u8_8x8(uint8_t *s, int p, const uint8x8_t s0,
|
|||
s += p;
|
||||
}
|
||||
|
||||
/* These intrinsics require immediate values, so we must use #defines
|
||||
to enforce that. */
|
||||
#define load_u8_4x1(s, s0, lane) \
|
||||
do { \
|
||||
*(s0) = vreinterpret_u8_u32( \
|
||||
vld1_lane_u32((uint32_t *)(s), vreinterpret_u32_u8(*(s0)), lane)); \
|
||||
} while (0)
|
||||
|
||||
static INLINE void load_u8_8x8(const uint8_t *s, ptrdiff_t p,
|
||||
uint8x8_t *const s0, uint8x8_t *const s1,
|
||||
uint8x8_t *const s2, uint8x8_t *const s3,
|
||||
|
|
@ -128,6 +136,13 @@ static INLINE void load_s16_4x4(const int16_t *s, ptrdiff_t p,
|
|||
*s3 = vld1_s16(s);
|
||||
}
|
||||
|
||||
/* These intrinsics require immediate values, so we must use #defines
|
||||
to enforce that. */
|
||||
#define store_u8_4x1(s, s0, lane) \
|
||||
do { \
|
||||
vst1_lane_u32((uint32_t *)(s), vreinterpret_u32_u8(s0), lane); \
|
||||
} while (0)
|
||||
|
||||
static INLINE void store_u8_8x8(uint8_t *s, ptrdiff_t p, const uint8x8_t s0,
|
||||
const uint8x8_t s1, const uint8x8_t s2,
|
||||
const uint8x8_t s3, const uint8x8_t s4,
|
||||
|
|
@ -242,6 +257,30 @@ static INLINE void store_s16_8x8(int16_t *s, ptrdiff_t dst_stride,
|
|||
vst1q_s16(s, s7);
|
||||
}
|
||||
|
||||
static INLINE void store_s16_4x4(int16_t *s, ptrdiff_t dst_stride,
|
||||
const int16x4_t s0, const int16x4_t s1,
|
||||
const int16x4_t s2, const int16x4_t s3) {
|
||||
vst1_s16(s, s0);
|
||||
s += dst_stride;
|
||||
vst1_s16(s, s1);
|
||||
s += dst_stride;
|
||||
vst1_s16(s, s2);
|
||||
s += dst_stride;
|
||||
vst1_s16(s, s3);
|
||||
}
|
||||
|
||||
static INLINE void store_s16_8x4(int16_t *s, ptrdiff_t dst_stride,
|
||||
const int16x8_t s0, const int16x8_t s1,
|
||||
const int16x8_t s2, const int16x8_t s3) {
|
||||
vst1q_s16(s, s0);
|
||||
s += dst_stride;
|
||||
vst1q_s16(s, s1);
|
||||
s += dst_stride;
|
||||
vst1q_s16(s, s2);
|
||||
s += dst_stride;
|
||||
vst1q_s16(s, s3);
|
||||
}
|
||||
|
||||
static INLINE void load_s16_8x8(const int16_t *s, ptrdiff_t p,
|
||||
int16x8_t *const s0, int16x8_t *const s1,
|
||||
int16x8_t *const s2, int16x8_t *const s3,
|
||||
|
|
@ -398,4 +437,49 @@ static INLINE void load_unaligned_u16_4x4(const uint16_t *buf, uint32_t stride,
|
|||
*tu1 = vsetq_lane_u64(a, *tu1, 1);
|
||||
}
|
||||
|
||||
static INLINE void load_s32_4x4(int32_t *s, int32_t p, int32x4_t *s1,
|
||||
int32x4_t *s2, int32x4_t *s3, int32x4_t *s4) {
|
||||
*s1 = vld1q_s32(s);
|
||||
s += p;
|
||||
*s2 = vld1q_s32(s);
|
||||
s += p;
|
||||
*s3 = vld1q_s32(s);
|
||||
s += p;
|
||||
*s4 = vld1q_s32(s);
|
||||
}
|
||||
|
||||
static INLINE void store_s32_4x4(int32_t *s, int32_t p, int32x4_t s1,
|
||||
int32x4_t s2, int32x4_t s3, int32x4_t s4) {
|
||||
vst1q_s32(s, s1);
|
||||
s += p;
|
||||
vst1q_s32(s, s2);
|
||||
s += p;
|
||||
vst1q_s32(s, s3);
|
||||
s += p;
|
||||
vst1q_s32(s, s4);
|
||||
}
|
||||
|
||||
static INLINE void load_u32_4x4(uint32_t *s, int32_t p, uint32x4_t *s1,
|
||||
uint32x4_t *s2, uint32x4_t *s3,
|
||||
uint32x4_t *s4) {
|
||||
*s1 = vld1q_u32(s);
|
||||
s += p;
|
||||
*s2 = vld1q_u32(s);
|
||||
s += p;
|
||||
*s3 = vld1q_u32(s);
|
||||
s += p;
|
||||
*s4 = vld1q_u32(s);
|
||||
}
|
||||
|
||||
static INLINE void store_u32_4x4(uint32_t *s, int32_t p, uint32x4_t s1,
|
||||
uint32x4_t s2, uint32x4_t s3, uint32x4_t s4) {
|
||||
vst1q_u32(s, s1);
|
||||
s += p;
|
||||
vst1q_u32(s, s2);
|
||||
s += p;
|
||||
vst1q_u32(s, s3);
|
||||
s += p;
|
||||
vst1q_u32(s, s4);
|
||||
}
|
||||
|
||||
#endif // AV1_COMMON_ARM_MEM_NEON_H_
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue