mirror of
https://repo.dactyloidae.xyz/Dactyloidae/UXP.git
synced 2026-09-27 02:47:31 +09:00
Update FFmpeg code to n3.2-65-gee56777
This commit is contained in:
trav90
Roy Tam
parent
c91ef9012b
commit
384e1e2734
66 changed files with 2760 additions and 806 deletions
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@ -24,36 +24,36 @@
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%include "libavutil/x86/x86util.asm"
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%include "vp9itxfm_template.asm"
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SECTION_RODATA
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SECTION_RODATA 32
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%macro VP9_IDCT_COEFFS 2-3 0
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const pw_m%1_%2
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times 4 dw -%1, %2
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times 8 dw -%1, %2
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const pw_%2_%1
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times 4 dw %2, %1
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times 8 dw %2, %1
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%if %3 == 1
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const pw_m%2_m%1
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times 4 dw -%2, -%1
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times 8 dw -%2, -%1
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%if %1 != %2
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const pw_m%2_%1
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times 4 dw -%2, %1
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times 8 dw -%2, %1
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const pw_%1_%2
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times 4 dw %1, %2
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times 8 dw %1, %2
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%endif
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%endif
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%if %1 < 11585
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pw_m%1x2: times 8 dw -%1*2
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pw_m%1x2: times 16 dw -%1*2
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%elif %1 > 11585
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pw_%1x2: times 8 dw %1*2
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pw_%1x2: times 16 dw %1*2
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%else
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const pw_%1x2
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times 8 dw %1*2
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times 16 dw %1*2
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%endif
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%if %2 != %1
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pw_%2x2: times 8 dw %2*2
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pw_%2x2: times 16 dw %2*2
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%endif
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%endmacro
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@ -127,16 +127,33 @@ SECTION .text
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%endmacro
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%macro VP9_STORE_2X 5-6 dstq ; reg1, reg2, tmp1, tmp2, zero, dst
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%if mmsize == 32
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pmovzxbw m%3, [%6]
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pmovzxbw m%4, [%6+strideq]
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%else
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movh m%3, [%6]
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movh m%4, [%6+strideq]
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punpcklbw m%3, m%5
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punpcklbw m%4, m%5
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%endif
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paddw m%3, m%1
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paddw m%4, m%2
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%if mmsize == 32
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packuswb m%3, m%4
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; Intel...
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vpermq m%3, m%3, q3120
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mova [%6], xm%3
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vextracti128 [%6+strideq], m%3, 1
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%elif mmsize == 16
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packuswb m%3, m%4
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movh [%6], m%3
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movhps [%6+strideq], m%3
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%else
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packuswb m%3, m%5
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packuswb m%4, m%5
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movh [%6], m%3
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movh [%6+strideq], m%4
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%endif
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%endmacro
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%macro ZERO_BLOCK 4 ; mem, stride, nnzcpl, zero_reg
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@ -1421,6 +1438,180 @@ VP9_IDCT_IDCT_16x16_ADD_XMM sse2
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VP9_IDCT_IDCT_16x16_ADD_XMM ssse3
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VP9_IDCT_IDCT_16x16_ADD_XMM avx
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%macro VP9_IDCT16_YMM_1D 0
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VP9_UNPACK_MULSUB_2W_4X 1, 15, 16305, 1606, [pd_8192], 0, 4 ; t8, t15
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VP9_UNPACK_MULSUB_2W_4X 9, 7, 10394, 12665, [pd_8192], 0, 4 ; t9, t14
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SUMSUB_BA w, 9, 1, 0 ; t8, t9
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SUMSUB_BA w, 7, 15, 0 ; t15, t14
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VP9_UNPACK_MULSUB_2W_4X 15, 1, 15137, 6270, [pd_8192], 0, 4 ; t9, t14
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VP9_UNPACK_MULSUB_2W_4X 5, 11, 14449, 7723, [pd_8192], 0, 4 ; t10, t13
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VP9_UNPACK_MULSUB_2W_4X 13, 3, 4756, 15679, [pd_8192], 0, 4 ; t11, t12
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SUMSUB_BA w, 5, 13, 0 ; t11, t10
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SUMSUB_BA w, 11, 3, 0 ; t12, t13
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VP9_UNPACK_MULSUB_2W_4X 3, 13, 6270, m15137, [pd_8192], 0, 4 ; t10, t13
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SUMSUB_BA w, 5, 9, 0 ; t8, t11
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SUMSUB_BA w, 3, 15, 0 ; t9, t10
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SUMSUB_BA w, 11, 7, 0 ; t15, t12
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SUMSUB_BA w, 13, 1, 0 ; t14, t13
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SUMSUB_BA w, 15, 1, 0
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SUMSUB_BA w, 9, 7, 0
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pmulhrsw m1, [pw_11585x2] ; t10
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pmulhrsw m7, [pw_11585x2] ; t11
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pmulhrsw m9, [pw_11585x2] ; t12
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pmulhrsw m15, [pw_11585x2] ; t13
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; even (tx8x8)
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mova m4, [blockq+128]
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mova [blockq+128], m5
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VP9_UNPACK_MULSUB_2W_4X 4, 12, 15137, 6270, [pd_8192], 0, 5 ; t2, t3
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VP9_UNPACK_MULSUB_2W_4X 2, 14, 16069, 3196, [pd_8192], 0, 5 ; t4, t7
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VP9_UNPACK_MULSUB_2W_4X 10, 6, 9102, 13623, [pd_8192], 0, 5 ; t5, t6
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mova m0, [blockq+ 0]
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SUMSUB_BA w, 8, 0, 5
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pmulhrsw m8, [pw_11585x2] ; t0
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pmulhrsw m0, [pw_11585x2] ; t1
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SUMSUB_BA w, 10, 2, 5 ; t4, t5
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SUMSUB_BA w, 6, 14, 5 ; t7, t6
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SUMSUB_BA w, 12, 8, 5 ; t0, t3
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SUMSUB_BA w, 4, 0, 5 ; t1, t2
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SUMSUB_BA w, 2, 14, 5
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pmulhrsw m14, [pw_11585x2] ; t5
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pmulhrsw m2, [pw_11585x2] ; t6
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SUMSUB_BA w, 6, 12, 5 ; t0, t7
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SUMSUB_BA w, 2, 4, 5 ; t1, t6
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SUMSUB_BA w, 14, 0, 5 ; t2, t5
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SUMSUB_BA w, 10, 8, 5 ; t3, t4
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; final stage
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SUMSUB_BA w, 11, 6, 5 ; out0, out15
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SUMSUB_BA w, 13, 2, 5 ; out1, out14
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SUMSUB_BA w, 15, 14, 5 ; out2, out13
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SUMSUB_BA w, 9, 10, 5 ; out3, out12
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SUMSUB_BA w, 7, 8, 5 ; out4, out11
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SUMSUB_BA w, 1, 0, 5 ; out5, out10
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SUMSUB_BA w, 3, 4, 5 ; out6, out9
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mova m5, [blockq+128]
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mova [blockq+192], m3
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SUMSUB_BA w, 5, 12, 3 ; out7, out8
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SWAP 0, 11, 8, 12, 10
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SWAP 1, 13, 14, 2, 15, 6, 3, 9, 4, 7, 5
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%endmacro
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; this is almost identical to VP9_STORE_2X, but it does two rows
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; for slightly improved interleaving, and it omits vpermq since the
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; input is DC so all values are identical
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%macro VP9_STORE_YMM_DC_4X 6 ; reg, tmp1, tmp2, tmp3, tmp4, zero
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mova xm%2, [dstq]
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mova xm%4, [dstq+strideq*2]
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vinserti128 m%2, m%2, [dstq+strideq], 1
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vinserti128 m%4, m%4, [dstq+stride3q], 1
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punpckhbw m%3, m%2, m%6
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punpcklbw m%2, m%6
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punpckhbw m%5, m%4, m%6
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punpcklbw m%4, m%6
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paddw m%3, m%1
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paddw m%2, m%1
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paddw m%5, m%1
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paddw m%4, m%1
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packuswb m%2, m%3
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packuswb m%4, m%5
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mova [dstq], xm%2
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mova [dstq+strideq*2], xm%4
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vextracti128 [dstq+strideq], m%2, 1
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vextracti128 [dstq+stride3q], m%4, 1
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%endmacro
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%if ARCH_X86_64 && HAVE_AVX2_EXTERNAL
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INIT_YMM avx2
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cglobal vp9_idct_idct_16x16_add, 4, 4, 16, dst, stride, block, eob
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cmp eobd, 1 ; faster path for when only DC is set
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jg .idctfull
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; dc-only
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mova m1, [pw_11585x2]
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vpbroadcastw m0, [blockq]
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pmulhrsw m0, m1
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pmulhrsw m0, m1
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pxor m5, m5
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pmulhrsw m0, [pw_512]
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movd [blockq], xm5
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DEFINE_ARGS dst, stride, stride3, cnt
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mov cntd, 4
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lea stride3q, [strideq*3]
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.loop_dc:
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VP9_STORE_YMM_DC_4X 0, 1, 2, 3, 4, 5
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lea dstq, [dstq+4*strideq]
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dec cntd
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jg .loop_dc
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RET
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DEFINE_ARGS dst, stride, block, eob
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.idctfull:
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mova m1, [blockq+ 32]
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mova m2, [blockq+ 64]
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mova m3, [blockq+ 96]
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mova m5, [blockq+160]
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mova m6, [blockq+192]
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mova m7, [blockq+224]
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mova m8, [blockq+256]
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mova m9, [blockq+288]
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mova m10, [blockq+320]
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mova m11, [blockq+352]
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mova m12, [blockq+384]
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mova m13, [blockq+416]
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mova m14, [blockq+448]
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mova m15, [blockq+480]
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VP9_IDCT16_YMM_1D
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TRANSPOSE16x16W 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
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[blockq+192], [blockq+128], 1
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mova [blockq+ 0], m0
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VP9_IDCT16_YMM_1D
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mova [blockq+224], m7
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mova [blockq+480], m15
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pxor m15, m15
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; store
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VP9_IDCT8_WRITEx2 0, 1, 6, 7, 15, [pw_512], 6
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lea dstq, [dstq+2*strideq]
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VP9_IDCT8_WRITEx2 2, 3, 6, 7, 15, [pw_512], 6
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lea dstq, [dstq+2*strideq]
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VP9_IDCT8_WRITEx2 4, 5, 6, 7, 15, [pw_512], 6
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lea dstq, [dstq+2*strideq]
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mova m6, [blockq+192]
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mova m7, [blockq+224]
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SWAP 0, 15
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mova m15, [blockq+480]
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VP9_IDCT8_WRITEx2 6, 7, 1, 2, 0, [pw_512], 6
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lea dstq, [dstq+2*strideq]
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VP9_IDCT8_WRITEx2 8, 9, 1, 2, 0, [pw_512], 6
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lea dstq, [dstq+2*strideq]
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VP9_IDCT8_WRITEx2 10, 11, 1, 2, 0, [pw_512], 6
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lea dstq, [dstq+2*strideq]
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VP9_IDCT8_WRITEx2 12, 13, 1, 2, 0, [pw_512], 6
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lea dstq, [dstq+2*strideq]
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VP9_IDCT8_WRITEx2 14, 15, 1, 2, 0, [pw_512], 6
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lea dstq, [dstq+2*strideq]
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; at the end of the loop, m0 should still be zero
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; use that to zero out block coefficients
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ZERO_BLOCK blockq, 32, 16, m0
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RET
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%endif
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;---------------------------------------------------------------------------------------------
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; void vp9_iadst_iadst_16x16_add_<opt>(uint8_t *dst, ptrdiff_t stride, int16_t *block, int eob);
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;---------------------------------------------------------------------------------------------
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@ -1801,7 +1992,12 @@ IADST16_FN iadst, IADST16, iadst, IADST16, avx
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;---------------------------------------------------------------------------------------------
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%macro VP9_IDCT32_1D 2-3 32 ; src, pass, nnzc
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%assign %%str 16*%2*%2
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%if %2 == 1
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%assign %%str mmsize
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%else
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%assign %%str 64
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%endif
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; first do t0-15, this can be done identical to idct16x16
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VP9_IDCT16_1D_START %1, %3/2, 64*2, tmpq, 2*%%str, 1
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@ -2096,17 +2292,125 @@ IADST16_FN iadst, IADST16, iadst, IADST16, avx
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mova m3, [tmpq+20*%%str] ; t5
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mova m13, [tmpq+24*%%str] ; t6
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SUMSUB_BA w, 6, 8, 10
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SUMSUB_BA w, 6, 8, 10
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mova [tmpq+ 3*%%str], m8 ; t15
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mova m10, [tmpq+28*%%str] ; t7
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SUMSUB_BA w, 0, 9, 8
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SUMSUB_BA w, 15, 12, 8
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SUMSUB_BA w, 14, 11, 8
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SUMSUB_BA w, 1, 2, 8
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SUMSUB_BA w, 7, 3, 8
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SUMSUB_BA w, 5, 13, 8
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mova m10, [tmpq+28*%%str] ; t7
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SUMSUB_BA w, 4, 10, 8
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%if cpuflag(avx2)
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; the "shitty" about this idct is that the final pass does the outermost
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; interleave sumsubs (t0/31, t1/30, etc) but the tN for the 16x16 need
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; to be sequential, which means I need to load/store half of the sumsub
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; intermediates back to/from memory to get a 16x16 transpose going...
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; This would be easier if we had more (e.g. 32) YMM regs here.
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mova [tmpq+ 7*%%str], m9
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mova [tmpq+11*%%str], m12
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mova [tmpq+15*%%str], m11
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mova [tmpq+19*%%str], m2
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mova [tmpq+23*%%str], m3
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mova [tmpq+27*%%str], m13
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mova [tmpq+31*%%str], m10
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mova [tmpq+12*%%str], m5
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mova m13, [tmpq+30*%%str] ; t8
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mova m12, [tmpq+26*%%str] ; t9
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mova m11, [tmpq+22*%%str] ; t10
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mova m10, [tmpq+18*%%str] ; t11
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mova m9, [tmpq+17*%%str] ; t20
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mova m8, [tmpq+ 1*%%str] ; t21
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mova m3, [tmpq+25*%%str] ; t22
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mova m2, [tmpq+ 5*%%str] ; t23
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SUMSUB_BA w, 9, 10, 5
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SUMSUB_BA w, 8, 11, 5
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SUMSUB_BA w, 3, 12, 5
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SUMSUB_BA w, 2, 13, 5
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mova [tmpq+ 1*%%str], m10
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mova [tmpq+ 5*%%str], m11
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mova [tmpq+17*%%str], m12
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mova [tmpq+25*%%str], m13
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mova m13, [tmpq+14*%%str] ; t12
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mova m12, [tmpq+10*%%str] ; t13
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mova m11, [tmpq+ 9*%%str] ; t18
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mova m10, [tmpq+13*%%str] ; t19
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SUMSUB_BA w, 11, 12, 5
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SUMSUB_BA w, 10, 13, 5
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mova [tmpq+ 9*%%str], m13
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mova [tmpq+13*%%str], m12
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mova [tmpq+10*%%str], m10
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mova [tmpq+14*%%str], m11
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mova m13, [tmpq+ 6*%%str] ; t14
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mova m12, [tmpq+ 2*%%str] ; t15
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mova m11, [tmpq+21*%%str] ; t16
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mova m10, [tmpq+29*%%str] ; t17
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SUMSUB_BA w, 11, 12, 5
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SUMSUB_BA w, 10, 13, 5
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mova [tmpq+21*%%str], m12
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mova [tmpq+29*%%str], m13
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mova m12, [tmpq+10*%%str]
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mova m13, [tmpq+14*%%str]
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TRANSPOSE16x16W 6, 0, 15, 14, 1, 7, 5, 4, \
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2, 3, 8, 9, 12, 13, 10, 11, \
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[tmpq+12*%%str], [tmpq+ 8*%%str], 1
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mova [tmpq+ 0*%%str], m6
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mova [tmpq+ 2*%%str], m0
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mova [tmpq+ 4*%%str], m15
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mova [tmpq+ 6*%%str], m14
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mova [tmpq+10*%%str], m7
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mova [tmpq+12*%%str], m5
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mova [tmpq+14*%%str], m4
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mova [tmpq+16*%%str], m2
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mova [tmpq+18*%%str], m3
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mova [tmpq+20*%%str], m8
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mova [tmpq+22*%%str], m9
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mova [tmpq+24*%%str], m12
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mova [tmpq+26*%%str], m13
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mova [tmpq+28*%%str], m10
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mova [tmpq+30*%%str], m11
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mova m0, [tmpq+21*%%str]
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mova m1, [tmpq+29*%%str]
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mova m2, [tmpq+13*%%str]
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mova m3, [tmpq+ 9*%%str]
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mova m4, [tmpq+ 1*%%str]
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mova m5, [tmpq+ 5*%%str]
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mova m7, [tmpq+25*%%str]
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mova m8, [tmpq+31*%%str]
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mova m9, [tmpq+27*%%str]
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mova m10, [tmpq+23*%%str]
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mova m11, [tmpq+19*%%str]
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mova m12, [tmpq+15*%%str]
|
||||
mova m13, [tmpq+11*%%str]
|
||||
mova m14, [tmpq+ 7*%%str]
|
||||
mova m15, [tmpq+ 3*%%str]
|
||||
TRANSPOSE16x16W 0, 1, 2, 3, 4, 5, 6, 7, \
|
||||
8, 9, 10, 11, 12, 13, 14, 15, \
|
||||
[tmpq+17*%%str], [tmpq+ 9*%%str], 1
|
||||
mova [tmpq+ 1*%%str], m0
|
||||
mova [tmpq+ 3*%%str], m1
|
||||
mova [tmpq+ 5*%%str], m2
|
||||
mova [tmpq+ 7*%%str], m3
|
||||
mova [tmpq+11*%%str], m5
|
||||
mova [tmpq+13*%%str], m6
|
||||
mova [tmpq+15*%%str], m7
|
||||
mova [tmpq+17*%%str], m8
|
||||
mova [tmpq+19*%%str], m9
|
||||
mova [tmpq+21*%%str], m10
|
||||
mova [tmpq+23*%%str], m11
|
||||
mova [tmpq+25*%%str], m12
|
||||
mova [tmpq+27*%%str], m13
|
||||
mova [tmpq+29*%%str], m14
|
||||
mova [tmpq+31*%%str], m15
|
||||
%else ; !avx2
|
||||
TRANSPOSE8x8W 6, 0, 15, 14, 1, 7, 5, 4, 8
|
||||
mova [tmpq+ 0*%%str], m6
|
||||
mova [tmpq+ 4*%%str], m0
|
||||
|
|
@ -2175,6 +2479,7 @@ IADST16_FN iadst, IADST16, iadst, IADST16, avx
|
|||
mova [tmpq+22*%%str], m13
|
||||
mova [tmpq+26*%%str], m14
|
||||
mova [tmpq+30*%%str], m15
|
||||
%endif ; avx2
|
||||
%else
|
||||
mova m2, [tmpq+24*%%str] ; t6
|
||||
mova m3, [tmpq+28*%%str] ; t7
|
||||
|
|
@ -2623,3 +2928,106 @@ cglobal vp9_idct_idct_32x32_add, 0, 6 + ARCH_X86_64 * 3, 16, 2048, dst, stride,
|
|||
VP9_IDCT_IDCT_32x32_ADD_XMM sse2
|
||||
VP9_IDCT_IDCT_32x32_ADD_XMM ssse3
|
||||
VP9_IDCT_IDCT_32x32_ADD_XMM avx
|
||||
|
||||
; this is almost identical to VP9_STORE_2X, but it does two rows
|
||||
; for slightly improved interleaving, and it omits vpermq since the
|
||||
; input is DC so all values are identical
|
||||
%macro VP9_STORE_YMM_DC_2X2 6 ; reg, tmp1, tmp2, tmp3, tmp4, zero
|
||||
mova m%2, [dstq]
|
||||
mova m%4, [dstq+strideq]
|
||||
punpckhbw m%3, m%2, m%6
|
||||
punpcklbw m%2, m%6
|
||||
punpckhbw m%5, m%4, m%6
|
||||
punpcklbw m%4, m%6
|
||||
paddw m%3, m%1
|
||||
paddw m%2, m%1
|
||||
paddw m%5, m%1
|
||||
paddw m%4, m%1
|
||||
packuswb m%2, m%3
|
||||
packuswb m%4, m%5
|
||||
mova [dstq+strideq*0], m%2
|
||||
mova [dstq+strideq*1], m%4
|
||||
%endmacro
|
||||
|
||||
%if ARCH_X86_64 && HAVE_AVX2_EXTERNAL
|
||||
INIT_YMM avx2
|
||||
cglobal vp9_idct_idct_32x32_add, 4, 9, 16, 2048, dst, stride, block, eob
|
||||
cmp eobd, 135
|
||||
jg .idctfull
|
||||
cmp eobd, 1
|
||||
jg .idct16x16
|
||||
|
||||
; dc-only case
|
||||
mova m1, [pw_11585x2]
|
||||
vpbroadcastw m0, [blockq]
|
||||
pmulhrsw m0, m1
|
||||
pmulhrsw m0, m1
|
||||
pxor m5, m5
|
||||
pmulhrsw m0, [pw_512]
|
||||
movd [blockq], xm5
|
||||
|
||||
DEFINE_ARGS dst, stride, cnt
|
||||
mov cntd, 16
|
||||
.loop_dc:
|
||||
VP9_STORE_YMM_DC_2X2 0, 1, 2, 3, 4, 5
|
||||
lea dstq, [dstq+2*strideq]
|
||||
dec cntd
|
||||
jg .loop_dc
|
||||
RET
|
||||
|
||||
DEFINE_ARGS dst_bak, stride, block, cnt, dst, stride30, dst_end, stride2, tmp
|
||||
.idct16x16:
|
||||
mov tmpq, rsp
|
||||
VP9_IDCT32_1D blockq, 1, 16
|
||||
|
||||
mov stride30q, strideq ; stride
|
||||
lea stride2q, [strideq*2] ; stride*2
|
||||
shl stride30q, 5 ; stride*32
|
||||
mov cntd, 2
|
||||
sub stride30q, stride2q ; stride*30
|
||||
.loop2_16x16:
|
||||
mov dstq, dst_bakq
|
||||
lea dst_endq, [dstq+stride30q]
|
||||
VP9_IDCT32_1D tmpq, 2, 16
|
||||
add dst_bakq, 16
|
||||
add tmpq, 32
|
||||
dec cntd
|
||||
jg .loop2_16x16
|
||||
|
||||
; at the end of the loop, m1 should still be zero
|
||||
; use that to zero out block coefficients
|
||||
ZERO_BLOCK blockq, 64, 16, m1
|
||||
RET
|
||||
|
||||
.idctfull:
|
||||
mov cntd, 2
|
||||
mov tmpq, rsp
|
||||
.loop1_full:
|
||||
VP9_IDCT32_1D blockq, 1
|
||||
add blockq, 32
|
||||
add tmpq, 1024
|
||||
dec cntd
|
||||
jg .loop1_full
|
||||
|
||||
sub blockq, 64
|
||||
|
||||
mov stride30q, strideq ; stride
|
||||
lea stride2q, [strideq*2] ; stride*2
|
||||
shl stride30q, 5 ; stride*32
|
||||
mov cntd, 2
|
||||
mov tmpq, rsp
|
||||
sub stride30q, stride2q ; stride*30
|
||||
.loop2_full:
|
||||
mov dstq, dst_bakq
|
||||
lea dst_endq, [dstq+stride30q]
|
||||
VP9_IDCT32_1D tmpq, 2
|
||||
add dst_bakq, 16
|
||||
add tmpq, 32
|
||||
dec cntd
|
||||
jg .loop2_full
|
||||
|
||||
; at the end of the loop, m1 should still be zero
|
||||
; use that to zero out block coefficients
|
||||
ZERO_BLOCK blockq, 64, 32, m1
|
||||
RET
|
||||
%endif
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue