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3 changed files with 23 additions and 0 deletions
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@ -2378,6 +2378,8 @@ CodeGenerator::visitUnarySharedStub(LUnarySharedStub* lir)
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switch (jsop) {
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switch (jsop) {
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case JSOP_BITNOT:
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case JSOP_BITNOT:
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case JSOP_NEG:
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case JSOP_NEG:
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case JSOP_INC:
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case JSOP_DEC:
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emitSharedStub(ICStub::Kind::UnaryArith_Fallback, lir);
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emitSharedStub(ICStub::Kind::UnaryArith_Fallback, lir);
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break;
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break;
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case JSOP_CALLPROP:
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case JSOP_CALLPROP:
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@ -216,6 +216,16 @@ ICUnaryArith_Int32::Compiler::generateStubCode(MacroAssembler& masm)
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masm.branchTest32(Assembler::Zero, R0.valueReg(), Imm32(0x7fffffff), &failure);
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masm.branchTest32(Assembler::Zero, R0.valueReg(), Imm32(0x7fffffff), &failure);
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masm.negl(R0.valueReg());
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masm.negl(R0.valueReg());
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break;
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break;
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case JSOP_INC: {
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RegisterOrInt32Constant rval = RegisterOrInt32Constant(R0.valueReg());
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masm.inc32(&rval);
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break;
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}
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case JSOP_DEC: {
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RegisterOrInt32Constant rval = RegisterOrInt32Constant(R0.valueReg());
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masm.dec32(&rval);
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break;
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}
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default:
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default:
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MOZ_CRASH("Unexpected op");
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MOZ_CRASH("Unexpected op");
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}
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}
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@ -226,6 +226,17 @@ ICUnaryArith_Int32::Compiler::generateStubCode(MacroAssembler& masm)
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masm.branchTest32(Assembler::Zero, R0.payloadReg(), Imm32(0x7fffffff), &failure);
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masm.branchTest32(Assembler::Zero, R0.payloadReg(), Imm32(0x7fffffff), &failure);
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masm.negl(R0.payloadReg());
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masm.negl(R0.payloadReg());
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break;
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break;
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case JSOP_INC: {
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RegisterOrInt32Constant rval = RegisterOrInt32Constant(R0.payloadReg());
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masm.inc32(&rval);
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break;
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}
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case JSOP_DEC: {
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RegisterOrInt32Constant rval = RegisterOrInt32Constant(R0.payloadReg());
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masm.dec32(&rval);
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break;
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}
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default:
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default:
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MOZ_CRASH("Unexpected op");
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MOZ_CRASH("Unexpected op");
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}
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}
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