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Issue #2308 & #1240 Follow-up - Fill in missing JSOP_INC/DEC cases for Ion on Intel32/64.

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Brian Smith 2023-09-17 06:21:49 -05:00 • committed by roytam1
commit 2b637c564f
3 changed files with 23 additions and 0 deletions
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2
js/src/jit/CodeGenerator.cpp
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@ -2378,6 +2378,8 @@ CodeGenerator::visitUnarySharedStub(LUnarySharedStub* lir)
switch (jsop) {
case JSOP_BITNOT:
case JSOP_NEG:
case JSOP_INC:
case JSOP_DEC:
emitSharedStub(ICStub::Kind::UnaryArith_Fallback, lir);
break;
case JSOP_CALLPROP:

10
js/src/jit/x64/SharedIC-x64.cpp
View file

@ -216,6 +216,16 @@ ICUnaryArith_Int32::Compiler::generateStubCode(MacroAssembler& masm)
masm.branchTest32(Assembler::Zero, R0.valueReg(), Imm32(0x7fffffff), &failure);
masm.negl(R0.valueReg());
break;
case JSOP_INC: {
RegisterOrInt32Constant rval = RegisterOrInt32Constant(R0.valueReg());
masm.inc32(&rval);
break;
}
case JSOP_DEC: {
RegisterOrInt32Constant rval = RegisterOrInt32Constant(R0.valueReg());
masm.dec32(&rval);
break;
}
default:
MOZ_CRASH("Unexpected op");
}

11
js/src/jit/x86/SharedIC-x86.cpp
View file

@ -226,6 +226,17 @@ ICUnaryArith_Int32::Compiler::generateStubCode(MacroAssembler& masm)
masm.branchTest32(Assembler::Zero, R0.payloadReg(), Imm32(0x7fffffff), &failure);
masm.negl(R0.payloadReg());
break;
case JSOP_INC: {
RegisterOrInt32Constant rval = RegisterOrInt32Constant(R0.payloadReg());
masm.inc32(&rval);
break;
}
case JSOP_DEC: {
RegisterOrInt32Constant rval = RegisterOrInt32Constant(R0.payloadReg());
masm.dec32(&rval);
break;
}
default:
MOZ_CRASH("Unexpected op");
}