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Issue #3049 - loongarch64: trim non-JIT PR fallout

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Basilisk-Dev 2026-04-26 14:34:35 -04:00 • committed by wuggy
commit 1b904254ce
7 changed files with 33 additions and 28 deletions
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2
js/src/jit/loongarch64/Architecture-loongarch64.cpp
View file

@ -73,7 +73,7 @@ uint32_t FloatRegister::getRegisterDumpOffsetInBytes() {
}
bool CPUFlagsHaveBeenComputed() {
// No optional LoongArch64 CPU feature bits are consumed by this backend yet.
// TODO(loongarch64): Add CPU flags support.
return true;
}

3
js/src/jit/loongarch64/Architecture-loongarch64.h
View file

@ -293,8 +293,7 @@ class FloatRegisters {
static const SetType AllDoubleMask = AllPhysMask * SpreadDouble;
static const SetType NoneMask = SetType(0);
// LoongArch64 only tracks the scalar callee-saved fp registers here; there
// are no SIMD aliases to account for in this backend yet.
// TODO(loongarch64): Much less than ARM64 here.
static const SetType NonVolatileMask =
SetType((1 << FloatRegisters::f24) | (1 << FloatRegisters::f25) |
(1 << FloatRegisters::f26) | (1 << FloatRegisters::f27) |

12
js/src/jit/loongarch64/Assembler-loongarch64.cpp
View file

@ -49,10 +49,11 @@ void js::jit::PatchJump(CodeLocationJump& jump_, CodeLocationLabel label,
// Note this is used for inter-wasm calls and may pass arguments and results
// in floating point registers even if the system ABI does not.
// For the internal JIT ABI we spill floating-point arguments beyond f0-f7 to
// the stack instead of recycling integer argument registers. Caller and callee
// both use this discipline, so it remains self-consistent even though the
// native LoongArch C ABI would next use integer argument slots.
// TODO(loongarch64): Inconsistent with LoongArch's calling convention.
// LoongArch floating-point parameters calling convention:
// The first eight floating-point parameters should be passed in f0-f7, and
// the other floating point parameters will be passed like integer parameters.
// But we just pass the other floating-point parameters on stack here.
ABIArg ABIArgGenerator::next(MIRType type) {
switch (type) {
case MIRType::Int32:
@ -334,8 +335,7 @@ void AssemblerLOONGARCH64::WriteInstStatic(uint32_t x, uint32_t* dest) {
}
BufferOffset AssemblerLOONGARCH64::haltingAlign(int alignment) {
// Like ARM64, we currently pad with nops because there is no dedicated
// backend-specific halting fill sequence here yet.
// TODO(loongarch64): Implement a proper halting align.
return nopAlign(alignment);
}

14
js/src/jit/loongarch64/Assembler-loongarch64.h
View file

@ -237,8 +237,8 @@ static_assert(JitStackAlignment % sizeof(Value) == 0 &&
JitStackValueAlignment >= 1,
"Stack alignment should be a non-zero multiple of sizeof(Value)");
// The backend does not expose LSX/LASX registers yet, but wasm/JIT constant
// pools still assume 16-byte alignment for SIMD-sized data blobs.
// TODO(loongarch64): this is just a filler to prevent a build failure. The
// LoongArch SIMD alignment requirements still need to be explored.
static constexpr uint32_t SimdMemoryAlignment = 16;
static_assert(CodeAlignment % SimdMemoryAlignment == 0,
@ -258,7 +258,9 @@ static constexpr uint32_t WasmCheckedTailEntryOffset = 16u;
static constexpr Scale ScalePointer = TimesEight;
// LoongArch instruction encoding constants and operand field positions.
// TODO(loongarch64): Add LoongArch instruction types description.
// LoongArch instruction encoding constants.
static const uint32_t RJShift = 5;
static const uint32_t RJBits = 5;
static const uint32_t RKShift = 10;
@ -340,11 +342,11 @@ static const uint32_t BOffImm21Mask = ((1 << Imm21Bits) - 1) << Imm21Shift;
static const uint32_t BOffImm26Mask = ((1 << Imm26Bits) - 1) << Imm26Shift;
static const uint32_t RegMask = Registers::Total - 1;
// LoongArch break encodes a 10-bit immediate trap code.
// TODO(loongarch64) Change to syscall?
static const uint32_t MAX_BREAK_CODE = 1024 - 1;
static const uint32_t WASM_TRAP = 6; // BRK_OVERFLOW
// Forward declarations for decoded instruction wrappers.
// TODO(loongarch64) Change to LoongArch instruction type.
class Instruction;
class InstReg;
class InstImm;
@ -862,7 +864,7 @@ class LOONGBufferWithExecutableCopy : public LOONGBuffer {
class AssemblerLOONGARCH64 : public AssemblerShared {
public:
// Keep these aligned with the shared MacroAssembler condition space.
// TODO(loongarch64): Should we remove these conditions here?
enum Condition {
Equal,
NotEqual,

8
js/src/jit/loongarch64/MacroAssembler-loongarch64.cpp
View file

@ -883,6 +883,7 @@ void MacroAssemblerLOONGARCH64::ma_subPtrTestOverflow(Register rd, Register rj,
void MacroAssemblerLOONGARCH64::ma_subPtrTestOverflow(Register rd, Register rj,
Imm32 imm, Label* overflow) {
// TODO(loongarch64): Check subPtrTestOverflow
MOZ_ASSERT(imm.value != INT32_MIN);
ma_addPtrTestOverflow(rd, rj, Imm32(-imm.value), overflow);
}
@ -1221,8 +1222,8 @@ void MacroAssemblerLOONGARCH64::ma_cmp_set(Register rd, Register rj, ImmPtr imm,
void MacroAssemblerLOONGARCH64::ma_cmp_set(Register rd, Address address, Imm32 imm,
Condition c) {
// TODO(loongarch64): 32-bit ma_cmp_set?
SecondScratchRegisterScope scratch2(asMasm());
// Match the register/Imm32 helper by comparing a sign-extended 32-bit value.
ma_ld_w(scratch2, address);
ma_cmp_set(rd, Register(scratch2), imm, c);
}
@ -1773,7 +1774,8 @@ void MacroAssemblerLOONGARCH64::storeUnalignedFloat32(
append(access, store.getOffset(), asMasm().framePushed());
}
// Branches emitted from loongarch64-specific code paths.
// Branches when done from within loongarch-specific code.
// TODO(loongarch64) Optimize ma_b
void MacroAssemblerLOONGARCH64::ma_b(Register lhs, Register rhs, Label* label,
Condition c, JumpKind jumpKind) {
switch (c) {
@ -2442,7 +2444,7 @@ void MacroAssemblerLOONGARCH64Compat::wasmLoadI64Impl(
as_ldx_w(output.reg, memoryBase, ptr);
break;
case Scalar::Uint32:
// Register64 consumers expect the upper half to be cleared for Uint32.
// TODO(loongarch64): Why need zero-extension here?
as_ldx_wu(output.reg, memoryBase, ptr);
break;
case Scalar::Int64:

17
js/src/jit/mips-shared/CodeGenerator-mips-shared.cpp
View file

@ -2236,11 +2236,8 @@ void
CodeGeneratorMIPSShared::visitAsmJSCompareExchangeHeap(LAsmJSCompareExchangeHeap* ins)
{
#ifdef JS_CODEGEN_LOONGARCH64
// LoongArch64 provides its own lowering/codegen for this path. Keep the
// shared MIPS fallback out of the build because it relies on MIPS-specific
// helpers and temps.
(void)ins;
MOZ_CRASH("unreachable: loongarch64 overrides asm.js compareExchange codegen");
MOZ_CRASH("asm.js atomics are not supported on loongarch64 yet");
#else
MAsmJSCompareExchangeHeap* mir = ins->mir();
Scalar::Type vt = mir->access().type();
@ -2267,7 +2264,7 @@ CodeGeneratorMIPSShared::visitAsmJSAtomicExchangeHeap(LAsmJSAtomicExchangeHeap*
{
#ifdef JS_CODEGEN_LOONGARCH64
(void)ins;
MOZ_CRASH("unreachable: loongarch64 overrides asm.js atomic exchange codegen");
MOZ_CRASH("asm.js atomics are not supported on loongarch64 yet");
#else
MAsmJSAtomicExchangeHeap* mir = ins->mir();
Scalar::Type vt = mir->access().type();
@ -2573,7 +2570,7 @@ CodeGeneratorMIPSShared::atomicBinopToTypedIntArray(AtomicOp op, Scalar::Type ar
(void)offsetTemp;
(void)maskTemp;
(void)output;
MOZ_CRASH("unreachable: loongarch64 overrides asm.js atomic binop codegen");
MOZ_CRASH("asm.js atomics are not supported on loongarch64 yet");
#else
MOZ_ASSERT(flagTemp != InvalidReg);
MOZ_ASSERT_IF(arrayType == Scalar::Uint32, outTemp != InvalidReg);
@ -2756,7 +2753,7 @@ CodeGeneratorMIPSShared::atomicBinopToTypedIntArray(AtomicOp op, Scalar::Type ar
(void)valueTemp;
(void)offsetTemp;
(void)maskTemp;
MOZ_CRASH("unreachable: loongarch64 overrides Ion atomic binop codegen");
MOZ_CRASH("atomics are not supported on loongarch64 Ion yet");
#else
MOZ_ASSERT(flagTemp != InvalidReg);
@ -2860,7 +2857,7 @@ CodeGeneratorMIPSShared::visitWasmAddOffset(LWasmAddOffset* lir)
{
#ifdef JS_CODEGEN_LOONGARCH64
(void)lir;
MOZ_CRASH("unreachable: loongarch64 overrides wasm offset codegen");
MOZ_CRASH("wasm is not supported on loongarch64 yet");
#else
MWasmAddOffset* mir = lir->mir();
Register base = ToRegister(lir->base());
@ -2957,7 +2954,7 @@ CodeGeneratorMIPSShared::visitCompareExchangeTypedArrayElement(LCompareExchangeT
{
#ifdef JS_CODEGEN_LOONGARCH64
(void)lir;
MOZ_CRASH("unreachable: loongarch64 overrides Ion compareExchange codegen");
MOZ_CRASH("atomics are not supported on loongarch64 Ion yet");
#else
Register elements = ToRegister(lir->elements());
AnyRegister output = ToAnyRegister(lir->output());
@ -2989,7 +2986,7 @@ CodeGeneratorMIPSShared::visitAtomicExchangeTypedArrayElement(LAtomicExchangeTyp
{
#ifdef JS_CODEGEN_LOONGARCH64
(void)lir;
MOZ_CRASH("unreachable: loongarch64 overrides Ion atomic exchange codegen");
MOZ_CRASH("atomics are not supported on loongarch64 Ion yet");
#else
Register elements = ToRegister(lir->elements());
AnyRegister output = ToAnyRegister(lir->output());

5
js/src/wasm/WasmBaselineCompile.cpp
View file

@ -29,6 +29,7 @@
* - Tiered compilation (bug 1277562)
* - profiler support / devtools (bug 1286948)
* - SIMD
* - Atomics
*
* There are lots of machine dependencies here but they are pretty well isolated
* to a segment of the compiler. Many dependencies will eventually be factored
@ -1102,7 +1103,11 @@ class BaseCompiler
}
void loadConstI32(Register r, Stk& src) {
#if defined(JS_CODEGEN_LOONGARCH64)
masm.move32(Imm32(src.i32val()), r);
#else
masm.mov(ImmWord((uint32_t)src.i32val() & 0xFFFFFFFFU), r);
#endif
}
void loadMemI32(Register r, Stk& src) {