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Issue #3049 - loongarch64: remove remaining MIPS file diffs

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Basilisk-Dev 2026-04-26 16:02:15 -04:00 • committed by wuggy
commit 0b9bf2f657
7 changed files with 473 additions and 111 deletions
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13
js/src/jit/CodeGenerator.h
View file

@ -47,19 +47,6 @@ class OutOfLineCallPostWriteBarrier;
class OutOfLineCallPostWriteElementBarrier;
class OutOfLineIsCallable;
class OutOfLineIsConstructor;
class LSimdSplatX4;
class LSimd128Int;
class LSimd128Float;
class LSimdReinterpretCast;
class LSimdExtractElementI;
class LSimdExtractElementF;
class LSimdBinaryCompIx4;
class LSimdBinaryCompFx4;
class LSimdBinaryArithIx4;
class LSimdBinaryArithFx4;
class LSimdBinaryBitwise;
class LSimdGeneralShuffleI;
class LSimdGeneralShuffleF;
class OutOfLineRegExpMatcher;
class OutOfLineRegExpSearcher;
class OutOfLineRegExpTester;

72
js/src/jit/loongarch64/MacroAssembler-loongarch64.cpp
View file

@ -22,6 +22,78 @@
namespace js {
namespace jit {
BufferOffset
MacroAssemblerLOONGARCH64Compat::as_div(Register lhs, Register rhs)
{
pendingDivKind_ = PendingDivW;
pendingDivLhs_ = lhs;
pendingDivRhs_ = rhs;
return m_buffer.nextOffset();
}
BufferOffset
MacroAssemblerLOONGARCH64Compat::as_divu(Register lhs, Register rhs)
{
pendingDivKind_ = PendingDivWU;
pendingDivLhs_ = lhs;
pendingDivRhs_ = rhs;
return m_buffer.nextOffset();
}
BufferOffset
MacroAssemblerLOONGARCH64Compat::as_ddiv(Register lhs, Register rhs)
{
pendingDivKind_ = PendingDivD;
pendingDivLhs_ = lhs;
pendingDivRhs_ = rhs;
return m_buffer.nextOffset();
}
BufferOffset
MacroAssemblerLOONGARCH64Compat::as_ddivu(Register lhs, Register rhs)
{
pendingDivKind_ = PendingDivDU;
pendingDivLhs_ = lhs;
pendingDivRhs_ = rhs;
return m_buffer.nextOffset();
}
BufferOffset
MacroAssemblerLOONGARCH64Compat::as_mflo(Register dest)
{
switch (pendingDivKind_) {
case PendingDivW:
return as_div_w(dest, pendingDivLhs_, pendingDivRhs_);
case PendingDivWU:
return as_div_wu(dest, pendingDivLhs_, pendingDivRhs_);
case PendingDivD:
return as_div_d(dest, pendingDivLhs_, pendingDivRhs_);
case PendingDivDU:
return as_div_du(dest, pendingDivLhs_, pendingDivRhs_);
case PendingDivNone:
break;
}
MOZ_CRASH("mflo without pending div");
}
BufferOffset
MacroAssemblerLOONGARCH64Compat::as_mfhi(Register dest)
{
switch (pendingDivKind_) {
case PendingDivW:
return as_mod_w(dest, pendingDivLhs_, pendingDivRhs_);
case PendingDivWU:
return as_mod_wu(dest, pendingDivLhs_, pendingDivRhs_);
case PendingDivD:
return as_mod_d(dest, pendingDivLhs_, pendingDivRhs_);
case PendingDivDU:
return as_mod_du(dest, pendingDivLhs_, pendingDivRhs_);
case PendingDivNone:
break;
}
MOZ_CRASH("mfhi without pending div");
}
namespace {
static inline void MoveAtomicValue(MacroAssemblerLOONGARCH64Compat& masm,

387
js/src/jit/loongarch64/MacroAssembler-loongarch64.h
View file

@ -297,6 +297,23 @@ class MacroAssemblerLOONGARCH64 : public Assembler {
ma_li(scratch2, imm);
ma_add32TestCarry(cond, rd, rj, scratch2, overflow);
}
template <typename L>
void ma_addTestCarry(Register rd, Register rs, Register rt, L overflow) {
MOZ_ASSERT_IF(rd == rs, rt != rd);
SecondScratchRegisterScope scratch(asMasm());
MOZ_ASSERT(scratch != rs);
MOZ_ASSERT(scratch != rt);
as_add_d(rd, rs, rt);
as_sltu(scratch, rd, rd == rs ? rt : rs);
ma_b(Register(scratch), Register(scratch), overflow, Assembler::NonZero);
}
template <typename L>
void ma_addTestCarry(Register rd, Register rs, Imm32 imm, L overflow) {
ScratchRegisterScope scratch(asMasm());
MOZ_ASSERT(scratch != rs);
ma_li(scratch, imm);
ma_addTestCarry(rd, rs, Register(scratch), overflow);
}
// subtract
void ma_sub_w(Register rd, Register rj, Imm32 imm);
@ -627,10 +644,26 @@ class MacroAssemblerLOONGARCH64 : public Assembler {
class MacroAssembler;
class MacroAssemblerLOONGARCH64Compat : public MacroAssemblerLOONGARCH64 {
private:
enum PendingDivKind {
PendingDivNone,
PendingDivW,
PendingDivWU,
PendingDivD,
PendingDivDU
};
PendingDivKind pendingDivKind_;
Register pendingDivLhs_;
Register pendingDivRhs_;
public:
using MacroAssemblerLOONGARCH64::call;
MacroAssemblerLOONGARCH64Compat() {}
MacroAssemblerLOONGARCH64Compat()
: pendingDivKind_(PendingDivNone),
pendingDivLhs_(InvalidReg),
pendingDivRhs_(InvalidReg) {}
struct AutoPrepareForPatching {
explicit AutoPrepareForPatching(MacroAssemblerLOONGARCH64Compat&) {}
@ -704,6 +737,12 @@ class MacroAssemblerLOONGARCH64Compat : public MacroAssemblerLOONGARCH64 {
void mov(CodeLabel* label, Register dest) { ma_li(dest, label); }
void mov(Register src, Address dest) { storePtr(src, dest); }
void mov(Address src, Register dest) { loadPtr(src, dest); }
BufferOffset as_div(Register lhs, Register rhs);
BufferOffset as_divu(Register lhs, Register rhs);
BufferOffset as_ddiv(Register lhs, Register rhs);
BufferOffset as_ddivu(Register lhs, Register rhs);
BufferOffset as_mflo(Register dest);
BufferOffset as_mfhi(Register dest);
void writeDataRelocation(const Value& val) {
// Raw GC pointer relocations and Value relocations both end up in
@ -1288,6 +1327,34 @@ class MacroAssemblerLOONGARCH64Compat : public MacroAssemblerLOONGARCH64 {
void atomicEffectOp(int nbytes, AtomicOp op, Register value,
const BaseIndex& address, Register valueTemp,
Register offsetTemp, Register maskTemp);
void atomicEffectOp(int nbytes, AtomicOp op, Imm32 value,
const Address& address, Register flagTemp,
Register valueTemp, Register offsetTemp,
Register maskTemp) {
atomicEffectOp(nbytes, op, value, address, valueTemp, offsetTemp,
maskTemp);
}
void atomicEffectOp(int nbytes, AtomicOp op, Imm32 value,
const BaseIndex& address, Register flagTemp,
Register valueTemp, Register offsetTemp,
Register maskTemp) {
atomicEffectOp(nbytes, op, value, address, valueTemp, offsetTemp,
maskTemp);
}
void atomicEffectOp(int nbytes, AtomicOp op, Register value,
const Address& address, Register flagTemp,
Register valueTemp, Register offsetTemp,
Register maskTemp) {
atomicEffectOp(nbytes, op, value, address, valueTemp, offsetTemp,
maskTemp);
}
void atomicEffectOp(int nbytes, AtomicOp op, Register value,
const BaseIndex& address, Register flagTemp,
Register valueTemp, Register offsetTemp,
Register maskTemp) {
atomicEffectOp(nbytes, op, value, address, valueTemp, offsetTemp,
maskTemp);
}
void atomicFetchOp(int nbytes, bool signExtend, AtomicOp op, Imm32 value,
const Address& address, Register valueTemp,
@ -1301,6 +1368,324 @@ class MacroAssemblerLOONGARCH64Compat : public MacroAssemblerLOONGARCH64 {
void atomicFetchOp(int nbytes, bool signExtend, AtomicOp op, Register value,
const BaseIndex& address, Register valueTemp,
Register offsetTemp, Register maskTemp, Register output);
void atomicFetchOp(int nbytes, bool signExtend, AtomicOp op, Imm32 value,
const Address& address, Register flagTemp,
Register valueTemp, Register offsetTemp,
Register maskTemp, Register output) {
atomicFetchOp(nbytes, signExtend, op, value, address, valueTemp,
offsetTemp, maskTemp, output);
}
void atomicFetchOp(int nbytes, bool signExtend, AtomicOp op, Imm32 value,
const BaseIndex& address, Register flagTemp,
Register valueTemp, Register offsetTemp,
Register maskTemp, Register output) {
atomicFetchOp(nbytes, signExtend, op, value, address, valueTemp,
offsetTemp, maskTemp, output);
}
void atomicFetchOp(int nbytes, bool signExtend, AtomicOp op, Register value,
const Address& address, Register flagTemp,
Register valueTemp, Register offsetTemp,
Register maskTemp, Register output) {
atomicFetchOp(nbytes, signExtend, op, value, address, valueTemp,
offsetTemp, maskTemp, output);
}
void atomicFetchOp(int nbytes, bool signExtend, AtomicOp op, Register value,
const BaseIndex& address, Register flagTemp,
Register valueTemp, Register offsetTemp,
Register maskTemp, Register output) {
atomicFetchOp(nbytes, signExtend, op, value, address, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicFetchAdd8SignExtend(const S& value, const T& mem,
Register flagTemp, Register valueTemp,
Register offsetTemp, Register maskTemp,
Register output) {
atomicFetchOp(1, true, AtomicFetchAddOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicFetchAdd8ZeroExtend(const S& value, const T& mem,
Register flagTemp, Register valueTemp,
Register offsetTemp, Register maskTemp,
Register output) {
atomicFetchOp(1, false, AtomicFetchAddOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicFetchAdd16SignExtend(const S& value, const T& mem,
Register flagTemp, Register valueTemp,
Register offsetTemp, Register maskTemp,
Register output) {
atomicFetchOp(2, true, AtomicFetchAddOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicFetchAdd16ZeroExtend(const S& value, const T& mem,
Register flagTemp, Register valueTemp,
Register offsetTemp, Register maskTemp,
Register output) {
atomicFetchOp(2, false, AtomicFetchAddOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicFetchAdd32(const S& value, const T& mem, Register flagTemp,
Register valueTemp, Register offsetTemp,
Register maskTemp, Register output) {
atomicFetchOp(4, false, AtomicFetchAddOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicAdd8(const T& value, const S& mem, Register flagTemp,
Register valueTemp, Register offsetTemp, Register maskTemp) {
atomicEffectOp(1, AtomicFetchAddOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp);
}
template <typename T, typename S>
void atomicAdd16(const T& value, const S& mem, Register flagTemp,
Register valueTemp, Register offsetTemp, Register maskTemp) {
atomicEffectOp(2, AtomicFetchAddOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp);
}
template <typename T, typename S>
void atomicAdd32(const T& value, const S& mem, Register flagTemp,
Register valueTemp, Register offsetTemp, Register maskTemp) {
atomicEffectOp(4, AtomicFetchAddOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp);
}
template <typename T, typename S>
void atomicFetchSub8SignExtend(const S& value, const T& mem,
Register flagTemp, Register valueTemp,
Register offsetTemp, Register maskTemp,
Register output) {
atomicFetchOp(1, true, AtomicFetchSubOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicFetchSub8ZeroExtend(const S& value, const T& mem,
Register flagTemp, Register valueTemp,
Register offsetTemp, Register maskTemp,
Register output) {
atomicFetchOp(1, false, AtomicFetchSubOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicFetchSub16SignExtend(const S& value, const T& mem,
Register flagTemp, Register valueTemp,
Register offsetTemp, Register maskTemp,
Register output) {
atomicFetchOp(2, true, AtomicFetchSubOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicFetchSub16ZeroExtend(const S& value, const T& mem,
Register flagTemp, Register valueTemp,
Register offsetTemp, Register maskTemp,
Register output) {
atomicFetchOp(2, false, AtomicFetchSubOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicFetchSub32(const S& value, const T& mem, Register flagTemp,
Register valueTemp, Register offsetTemp,
Register maskTemp, Register output) {
atomicFetchOp(4, false, AtomicFetchSubOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicSub8(const T& value, const S& mem, Register flagTemp,
Register valueTemp, Register offsetTemp, Register maskTemp) {
atomicEffectOp(1, AtomicFetchSubOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp);
}
template <typename T, typename S>
void atomicSub16(const T& value, const S& mem, Register flagTemp,
Register valueTemp, Register offsetTemp, Register maskTemp) {
atomicEffectOp(2, AtomicFetchSubOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp);
}
template <typename T, typename S>
void atomicSub32(const T& value, const S& mem, Register flagTemp,
Register valueTemp, Register offsetTemp, Register maskTemp) {
atomicEffectOp(4, AtomicFetchSubOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp);
}
template <typename T, typename S>
void atomicFetchAnd8SignExtend(const S& value, const T& mem,
Register flagTemp, Register valueTemp,
Register offsetTemp, Register maskTemp,
Register output) {
atomicFetchOp(1, true, AtomicFetchAndOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicFetchAnd8ZeroExtend(const S& value, const T& mem,
Register flagTemp, Register valueTemp,
Register offsetTemp, Register maskTemp,
Register output) {
atomicFetchOp(1, false, AtomicFetchAndOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicFetchAnd16SignExtend(const S& value, const T& mem,
Register flagTemp, Register valueTemp,
Register offsetTemp, Register maskTemp,
Register output) {
atomicFetchOp(2, true, AtomicFetchAndOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicFetchAnd16ZeroExtend(const S& value, const T& mem,
Register flagTemp, Register valueTemp,
Register offsetTemp, Register maskTemp,
Register output) {
atomicFetchOp(2, false, AtomicFetchAndOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicFetchAnd32(const S& value, const T& mem, Register flagTemp,
Register valueTemp, Register offsetTemp,
Register maskTemp, Register output) {
atomicFetchOp(4, false, AtomicFetchAndOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicAnd8(const T& value, const S& mem, Register flagTemp,
Register valueTemp, Register offsetTemp, Register maskTemp) {
atomicEffectOp(1, AtomicFetchAndOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp);
}
template <typename T, typename S>
void atomicAnd16(const T& value, const S& mem, Register flagTemp,
Register valueTemp, Register offsetTemp, Register maskTemp) {
atomicEffectOp(2, AtomicFetchAndOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp);
}
template <typename T, typename S>
void atomicAnd32(const T& value, const S& mem, Register flagTemp,
Register valueTemp, Register offsetTemp, Register maskTemp) {
atomicEffectOp(4, AtomicFetchAndOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp);
}
template <typename T, typename S>
void atomicFetchOr8SignExtend(const S& value, const T& mem,
Register flagTemp, Register valueTemp,
Register offsetTemp, Register maskTemp,
Register output) {
atomicFetchOp(1, true, AtomicFetchOrOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicFetchOr8ZeroExtend(const S& value, const T& mem,
Register flagTemp, Register valueTemp,
Register offsetTemp, Register maskTemp,
Register output) {
atomicFetchOp(1, false, AtomicFetchOrOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicFetchOr16SignExtend(const S& value, const T& mem,
Register flagTemp, Register valueTemp,
Register offsetTemp, Register maskTemp,
Register output) {
atomicFetchOp(2, true, AtomicFetchOrOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicFetchOr16ZeroExtend(const S& value, const T& mem,
Register flagTemp, Register valueTemp,
Register offsetTemp, Register maskTemp,
Register output) {
atomicFetchOp(2, false, AtomicFetchOrOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicFetchOr32(const S& value, const T& mem, Register flagTemp,
Register valueTemp, Register offsetTemp,
Register maskTemp, Register output) {
atomicFetchOp(4, false, AtomicFetchOrOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicOr8(const T& value, const S& mem, Register flagTemp,
Register valueTemp, Register offsetTemp, Register maskTemp) {
atomicEffectOp(1, AtomicFetchOrOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp);
}
template <typename T, typename S>
void atomicOr16(const T& value, const S& mem, Register flagTemp,
Register valueTemp, Register offsetTemp, Register maskTemp) {
atomicEffectOp(2, AtomicFetchOrOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp);
}
template <typename T, typename S>
void atomicOr32(const T& value, const S& mem, Register flagTemp,
Register valueTemp, Register offsetTemp, Register maskTemp) {
atomicEffectOp(4, AtomicFetchOrOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp);
}
template <typename T, typename S>
void atomicFetchXor8SignExtend(const S& value, const T& mem,
Register flagTemp, Register valueTemp,
Register offsetTemp, Register maskTemp,
Register output) {
atomicFetchOp(1, true, AtomicFetchXorOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicFetchXor8ZeroExtend(const S& value, const T& mem,
Register flagTemp, Register valueTemp,
Register offsetTemp, Register maskTemp,
Register output) {
atomicFetchOp(1, false, AtomicFetchXorOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicFetchXor16SignExtend(const S& value, const T& mem,
Register flagTemp, Register valueTemp,
Register offsetTemp, Register maskTemp,
Register output) {
atomicFetchOp(2, true, AtomicFetchXorOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicFetchXor16ZeroExtend(const S& value, const T& mem,
Register flagTemp, Register valueTemp,
Register offsetTemp, Register maskTemp,
Register output) {
atomicFetchOp(2, false, AtomicFetchXorOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicFetchXor32(const S& value, const T& mem, Register flagTemp,
Register valueTemp, Register offsetTemp,
Register maskTemp, Register output) {
atomicFetchOp(4, false, AtomicFetchXorOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp, output);
}
template <typename T, typename S>
void atomicXor8(const T& value, const S& mem, Register flagTemp,
Register valueTemp, Register offsetTemp, Register maskTemp) {
atomicEffectOp(1, AtomicFetchXorOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp);
}
template <typename T, typename S>
void atomicXor16(const T& value, const S& mem, Register flagTemp,
Register valueTemp, Register offsetTemp, Register maskTemp) {
atomicEffectOp(2, AtomicFetchXorOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp);
}
template <typename T, typename S>
void atomicXor32(const T& value, const S& mem, Register flagTemp,
Register valueTemp, Register offsetTemp, Register maskTemp) {
atomicEffectOp(4, AtomicFetchXorOp, value, mem, flagTemp, valueTemp,
offsetTemp, maskTemp);
}
void compareExchange(int nbytes, bool signExtend, const Address& address,
Register oldval, Register newval, Register valueTemp,

72
js/src/jit/mips-shared/CodeGenerator-mips-shared.cpp
View file

@ -136,7 +136,7 @@ CodeGeneratorMIPSShared::visitCompare(LCompare* comp)
const LAllocation* right = comp->getOperand(1);
const LDefinition* def = comp->getDef(0);
#if defined(JS_CODEGEN_MIPS64) || defined(JS_CODEGEN_LOONGARCH64)
#ifdef JS_CODEGEN_MIPS64
if (mir->compareType() == MCompare::Compare_Object) {
if (right->isGeneralReg())
masm.cmpPtrSet(cond, ToRegister(left), ToRegister(right), ToRegister(def));
@ -160,7 +160,7 @@ CodeGeneratorMIPSShared::visitCompareAndBranch(LCompareAndBranch* comp)
MCompare* mir = comp->cmpMir();
Assembler::Condition cond = JSOpToCondition(mir->compareType(), comp->jsop());
#if defined(JS_CODEGEN_MIPS64) || defined(JS_CODEGEN_LOONGARCH64)
#ifdef JS_CODEGEN_MIPS64
if (mir->compareType() == MCompare::Compare_Object) {
if (comp->right()->isGeneralReg()) {
emitBranch(ToRegister(comp->left()), ToRegister(comp->right()), cond,
@ -617,12 +617,8 @@ CodeGeneratorMIPSShared::visitDivI(LDivI* ins)
// All regular. Lets call div.
if (mir->canTruncateRemainder()) {
#ifdef JS_CODEGEN_LOONGARCH64
masm.as_div_w(dest, lhs, rhs);
#else
masm.as_div(lhs, rhs);
masm.as_mflo(dest);
#endif
} else {
MOZ_ASSERT(mir->fallible());
@ -753,12 +749,8 @@ CodeGeneratorMIPSShared::visitModI(LModI* ins)
masm.bind(&notNegative);
}
#ifdef JS_CODEGEN_LOONGARCH64
masm.as_mod_w(dest, lhs, rhs);
#else
masm.as_div(lhs, rhs);
masm.as_mfhi(dest);
#endif
// If X%Y == 0 and X < 0, then we *actually* wanted to return -0.0
if (mir->canBeNegativeDividend()) {
@ -2235,10 +2227,6 @@ CodeGeneratorMIPSShared::visitAsmJSStoreHeap(LAsmJSStoreHeap* ins)
void
CodeGeneratorMIPSShared::visitAsmJSCompareExchangeHeap(LAsmJSCompareExchangeHeap* ins)
{
#ifdef JS_CODEGEN_LOONGARCH64
(void)ins;
MOZ_CRASH("asm.js atomics are not supported on loongarch64 yet");
#else
MAsmJSCompareExchangeHeap* mir = ins->mir();
Scalar::Type vt = mir->access().type();
const LAllocation* ptr = ins->ptr();
@ -2256,16 +2244,11 @@ CodeGeneratorMIPSShared::visitAsmJSCompareExchangeHeap(LAsmJSCompareExchangeHeap
srcAddr, oldval, newval, InvalidReg,
valueTemp, offsetTemp, maskTemp,
ToAnyRegister(ins->output()));
#endif
}
void
CodeGeneratorMIPSShared::visitAsmJSAtomicExchangeHeap(LAsmJSAtomicExchangeHeap* ins)
{
#ifdef JS_CODEGEN_LOONGARCH64
(void)ins;
MOZ_CRASH("asm.js atomics are not supported on loongarch64 yet");
#else
MAsmJSAtomicExchangeHeap* mir = ins->mir();
Scalar::Type vt = mir->access().type();
Register ptrReg = ToRegister(ins->ptr());
@ -2280,7 +2263,6 @@ CodeGeneratorMIPSShared::visitAsmJSAtomicExchangeHeap(LAsmJSAtomicExchangeHeap*
masm.atomicExchangeToTypedIntArray(vt == Scalar::Uint32 ? Scalar::Int32 : vt,
srcAddr, value, InvalidReg, valueTemp,
offsetTemp, maskTemp, ToAnyRegister(ins->output()));
#endif
}
void
@ -2458,24 +2440,15 @@ CodeGeneratorMIPSShared::visitUDivOrMod(LUDivOrMod* ins)
}
}
#ifdef JS_CODEGEN_LOONGARCH64
masm.as_mod_wu(ScratchRegister, lhs, rhs);
masm.move32(ScratchRegister, output);
#else
masm.as_divu(lhs, rhs);
masm.as_mfhi(output);
#endif
// If the remainder is > 0, bailout since this must be a double.
if (ins->mir()->isDiv()) {
if (!ins->mir()->toDiv()->canTruncateRemainder())
bailoutCmp32(Assembler::NonZero, output, output, ins->snapshot());
// Get quotient
#ifdef JS_CODEGEN_LOONGARCH64
masm.as_div_wu(output, lhs, rhs);
#else
masm.as_mflo(output);
#endif
}
if (!ins->mir()->isTruncated())
@ -2559,19 +2532,6 @@ CodeGeneratorMIPSShared::atomicBinopToTypedIntArray(AtomicOp op, Scalar::Type ar
Register offsetTemp, Register maskTemp,
AnyRegister output)
{
#ifdef JS_CODEGEN_LOONGARCH64
(void)op;
(void)arrayType;
(void)value;
(void)mem;
(void)flagTemp;
(void)outTemp;
(void)valueTemp;
(void)offsetTemp;
(void)maskTemp;
(void)output;
MOZ_CRASH("asm.js atomics are not supported on loongarch64 yet");
#else
MOZ_ASSERT(flagTemp != InvalidReg);
MOZ_ASSERT_IF(arrayType == Scalar::Uint32, outTemp != InvalidReg);
@ -2709,7 +2669,6 @@ CodeGeneratorMIPSShared::atomicBinopToTypedIntArray(AtomicOp op, Scalar::Type ar
default:
MOZ_CRASH("Invalid typed array type");
}
#endif
}
template void
@ -2744,17 +2703,6 @@ CodeGeneratorMIPSShared::atomicBinopToTypedIntArray(AtomicOp op, Scalar::Type ar
const T& mem, Register flagTemp, Register valueTemp,
Register offsetTemp, Register maskTemp)
{
#ifdef JS_CODEGEN_LOONGARCH64
(void)op;
(void)arrayType;
(void)value;
(void)mem;
(void)flagTemp;
(void)valueTemp;
(void)offsetTemp;
(void)maskTemp;
MOZ_CRASH("atomics are not supported on loongarch64 Ion yet");
#else
MOZ_ASSERT(flagTemp != InvalidReg);
switch (arrayType) {
@ -2827,7 +2775,6 @@ CodeGeneratorMIPSShared::atomicBinopToTypedIntArray(AtomicOp op, Scalar::Type ar
default:
MOZ_CRASH("Invalid typed array type");
}
#endif
}
template void
@ -2855,16 +2802,11 @@ CodeGeneratorMIPSShared::atomicBinopToTypedIntArray(AtomicOp op, Scalar::Type ar
void
CodeGeneratorMIPSShared::visitWasmAddOffset(LWasmAddOffset* lir)
{
#ifdef JS_CODEGEN_LOONGARCH64
(void)lir;
MOZ_CRASH("wasm is not supported on loongarch64 yet");
#else
MWasmAddOffset* mir = lir->mir();
Register base = ToRegister(lir->base());
Register out = ToRegister(lir->output());
masm.ma_addTestCarry(out, base, Imm32(mir->offset()), trap(mir, wasm::Trap::OutOfBounds));
#endif
}
template <typename T>
@ -2952,10 +2894,6 @@ CodeGeneratorMIPSShared::visitAtomicTypedArrayElementBinopForEffect(LAtomicTyped
void
CodeGeneratorMIPSShared::visitCompareExchangeTypedArrayElement(LCompareExchangeTypedArrayElement* lir)
{
#ifdef JS_CODEGEN_LOONGARCH64
(void)lir;
MOZ_CRASH("atomics are not supported on loongarch64 Ion yet");
#else
Register elements = ToRegister(lir->elements());
AnyRegister output = ToAnyRegister(lir->output());
Register temp = lir->temp()->isBogusTemp() ? InvalidReg : ToRegister(lir->temp());
@ -2978,16 +2916,11 @@ CodeGeneratorMIPSShared::visitCompareExchangeTypedArrayElement(LCompareExchangeT
masm.compareExchangeToTypedIntArray(arrayType, dest, oldval, newval, temp,
valueTemp, offsetTemp, maskTemp, output);
}
#endif
}
void
CodeGeneratorMIPSShared::visitAtomicExchangeTypedArrayElement(LAtomicExchangeTypedArrayElement* lir)
{
#ifdef JS_CODEGEN_LOONGARCH64
(void)lir;
MOZ_CRASH("atomics are not supported on loongarch64 Ion yet");
#else
Register elements = ToRegister(lir->elements());
AnyRegister output = ToAnyRegister(lir->output());
Register temp = lir->temp()->isBogusTemp() ? InvalidReg : ToRegister(lir->temp());
@ -3009,5 +2942,4 @@ CodeGeneratorMIPSShared::visitAtomicExchangeTypedArrayElement(LAtomicExchangeTyp
masm.atomicExchangeToTypedIntArray(arrayType, dest, value, temp,
valueTemp, offsetTemp, maskTemp, output);
}
#endif
}

13
js/src/jit/mips-shared/CodeGenerator-mips-shared.h
View file

@ -13,19 +13,6 @@ namespace jit {
class OutOfLineBailout;
class OutOfLineTableSwitch;
class LSimdSplatX4;
class LSimd128Int;
class LSimd128Float;
class LSimdReinterpretCast;
class LSimdExtractElementI;
class LSimdExtractElementF;
class LSimdBinaryCompIx4;
class LSimdBinaryCompFx4;
class LSimdBinaryArithIx4;
class LSimdBinaryArithFx4;
class LSimdBinaryBitwise;
class LSimdGeneralShuffleI;
class LSimdGeneralShuffleF;
class CodeGeneratorMIPSShared : public CodeGeneratorShared
{

14
js/src/jit/mips64/CodeGenerator-mips64.cpp
View file

@ -383,19 +383,12 @@ CodeGeneratorMIPS64::visitDivOrModI64(LDivOrModI64* lir)
masm.bind(&notmin);
}
#ifdef JS_CODEGEN_LOONGARCH64
if (lir->mir()->isMod())
masm.as_mod_d(output, lhs, rhs);
else
masm.as_div_d(output, lhs, rhs);
#else
masm.as_ddiv(lhs, rhs);
if (lir->mir()->isMod())
masm.as_mfhi(output);
else
masm.as_mflo(output);
#endif
masm.bind(&done);
}
@ -413,19 +406,12 @@ CodeGeneratorMIPS64::visitUDivOrModI64(LUDivOrModI64* lir)
if (lir->canBeDivideByZero())
masm.ma_b(rhs, rhs, trap(lir, wasm::Trap::IntegerDivideByZero), Assembler::Zero);
#ifdef JS_CODEGEN_LOONGARCH64
if (lir->mir()->isMod())
masm.as_mod_du(output, lhs, rhs);
else
masm.as_div_du(output, lhs, rhs);
#else
masm.as_ddivu(lhs, rhs);
if (lir->mir()->isMod())
masm.as_mfhi(output);
else
masm.as_mflo(output);
#endif
masm.bind(&done);
}

13
js/src/jit/shared/CodeGenerator-shared.h
View file

@ -27,6 +27,19 @@ class OutOfLineCode;
class CodeGenerator;
class MacroAssembler;
class IonCache;
class LSimdSplatX4;
class LSimd128Int;
class LSimd128Float;
class LSimdReinterpretCast;
class LSimdExtractElementI;
class LSimdExtractElementF;
class LSimdBinaryCompIx4;
class LSimdBinaryCompFx4;
class LSimdBinaryArithIx4;
class LSimdBinaryArithFx4;
class LSimdBinaryBitwise;
class LSimdGeneralShuffleI;
class LSimdGeneralShuffleF;
template <class ArgSeq, class StoreOutputTo>
class OutOfLineCallVM;