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Nishi 2026-08-03 03:28:56 +09:00
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Bus Specification Revision 1.0
This bus is intended for expansion boards connected to the CPU board.
Top view of CPU board connectors
(two 2x20 2.54 mm stacking headers/sockets)
Note that the PCB edge is at the top of this diagram.
Left connector
| 1| 2| 3| 4| 5| 6| 7| 8| 9| 10| 11| 12| 13| 14| 15| 16| 17| 18| 19| 20|
| A23| A22| A21| A20| A19| A18| A17| A16| A15| A14| GND| A13| A12| A11| A10| A09| A08| A07| A06| A05|
| A04| A03| A02| A01| GND| AS| R/W| UDS| LDS| GND| RESET| HALT| CLK| DTACK| GND| RES| RES| RES| 5V| 5V|
| 21| 22| 23| 24| 25| 26| 27| 28| 29| 30| 31| 32| 33| 34| 35| 36| 37| 38| 39| 40|
Middle connector
| 1| 2| 3| 4| 5| 6| 7| 8| 9| 10| 11| 12| 13| 14| 15| 16| 17| 18| 19| 20|
| D15| D14| D13| D12| D11| D10| D09| D08| GND| D07| D06| D05| D04| D03| D02| D01| D00| GND| BR| BG|
| BGACK| BERR| GND| FC0| FC1| FC2| GND| RES| RES| RES| RES| RES| RES| RES| RES| RES| RES| RES| 5V| 5V|
| 21| 22| 23| 24| 25| 26| 27| 28| 29| 30| 31| 32| 33| 34| 35| 36| 37| 38| 39| 40|
Right connector
| 1| 2| 3| 4| 5| 6| 7| 8| 9| 10| 11| 12| 13| 14| 15| 16| 17| 18| 19| 20|
| /IO0| /IO1| /IO2| /IO3| GND| /IO4| /IO5| /IO6| /IO7| GND| /IRQ0| /IRQ1| /IRQ2| /IRQ3| GND| /IRQ4| /IRQ5| /IRQ6| /IRQ7| GND|
| /IACK0| /IACK1| /IACK2| /IACK3| GND| /IACK4| /IACK5| /IACK6| /IACK7| GND|/IOACK0|/IOACK1|/IOACK2|/IOACK3| GND|/IOACK4|/IOACK5|/IOACK6|/IOACK7| 5V|
| 21| 22| 23| 24| 25| 26| 27| 28| 29| 30| 31| 32| 33| 34| 35| 36| 37| 38| 39| 40|
Notes
/IO0-/IO7 are active-low chip select outputs generated by the CPU board.
/IRQ0-/IRQ7 are active-low interrupt request inputs to the CPU board.
/IACK0-/IACK7 are active-low interrupt acknowledge outputs generated by the CPU board.
/IOACK0-/IOACK7 are active-low I/O acknowledge inputs to the CPU board.
All other signals are the direct MC68000/MC68010 signals.
Consult the MC68000/MC68010 documentation set for their definitions and active polarity.
Signal Direction
------------------------------------------------
/IO0-/IO7 CPU board -> Expansion board
/IRQ0-/IRQ7 Expansion board -> CPU board
/IACK0-/IACK7 CPU board -> Expansion board
/IOACK Expansion board -> CPU board
Unless otherwise specified, all signals are 5 V TTL-compatible.
Expansion boards MUST only drive BR and BGACK in accordance with the MC68000 bus arbitration protocol.
Reserved pins MUST remain unconnected.